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PI7C9X130
PCI Express to PCI-X Reversible Bridge
Revision 1.2
3545 North First Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Internet: http://www.pericom.com
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC. 1) Life support devices or system are devices or systems which: a) Are intended for surgical implant into the body or b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation.
2)
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Page 2 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
REVISION HISTORY
Date
02/24/06 03/20/06
Revision Number
0.1 0.2
Description
First Draft of PI7C9X130 Data Sheet Correct INTA, B, C, D buffer type Update configuration map and registers Update JTAG chain order Add PCI/PCI-X selection information Update on configuration register bit definitions. 1) Bit [10, 7:2] of offset 40h 2) Bit [31:30] of offset 68h 3) Bit [0] of offset 70h 4) Bit [23:22] of offset 94h 5) Bit [7:1] of offset 164h Correct typo of pin CLKRUN_L in pin assignment and JTAG section. Add Absolute Maximum Ratings Correct pin description: 1. REQ_L as GPI and GNT_L as GPO 2. CLKOUT [8:0] as CLKOUT [6:0] Correct default setting for bit [31:30] of offset 68h Completed non-transparent function for address 28h - 2Bh in the Configuration Register Map - section 7.1 Corrected pin HSEN (R3) in section 2.6 - Miscellaneous Signals. Should read tie LOW if Hot Swap is not used instead of tie HIGH Revised table 8-1 in section 8 Address bit[5] corrected to equal 0 Address bit[4] corrected to equal GPIO[3] Revised PCIe Base Specification Compliancy from 1.0a to 1.1 Corrected pin HSSW (T3) in section 2.6 - Miscellaneous Signals. Remove "Tied high if hot swap function is not used." Corrected bit[13] offset 110h from reserved to "Advisory Non-Fatal Error Status" Changed Logos and some font types Corrected Pin #'s of GNT_L[1], GNT_L[2], GNT_[3], GNT_[4], GNT_[5] on Table 14-1JTAG Boundary Scan Register Definition Recommendation of Pull-up Resistor for PI7C9X130 Control Signals added to section 16.3 of PI7C9X130 Datasheets; pin numbers of SMBCLK and SMBDAT are corrected under section 5.2. Added PCIX Clock Detection to Chapter 9, Clock Scheme.
04/07/06
0.3
06/07/06
0.4
06/19/06 03/26/2007 04/18/2007
0.5 0.6 0.7
05/02/2007
0.8
05/15/2007 06/08/2007 07/13/2007 08/07/2007 09/28//2007
0.9 0.91 1.0 1.1 1.2
PREFACE
The datasheet of PI7C9X130 will be enhanced periodically when updated information is available. The technical information in this datasheet is subject to change without notice. This document describes the functionalities of PI7C9X130 (PCI Express Bridge) and provides technical information for designers to design their hardware using PI7C9X130.
Page 3 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
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Page 4 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
TABLE OF CONTENTS
1 INTRODUCTION .............................................................................................................................................13 1.1 1.2 1.3 2 PCI EXPRESS FEATURES........................................................................................................................13 PCI/PCI-X FEATURES ..............................................................................................................................14 GENERAL FEATURES .............................................................................................................................14
PIN DEFINITION .............................................................................................................................................15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 SIGNAL TYPES .........................................................................................................................................15 PCI EXPRESS SIGNALS ...........................................................................................................................15 PCI SIGNALS .............................................................................................................................................16 MODE SELECT AND STRAPPING SIGNALS........................................................................................18 JTAG BOUNDARY SCAN SIGNALS.......................................................................................................18 MISCELLANEOUS SIGNALS ..................................................................................................................19 POWER AND GROUND PINS ..................................................................................................................20 PIN ASSIGNMENT ....................................................................................................................................20
3
MODE SELECTION AND PIN STRAPPING ...............................................................................................22 3.1 3.2 3.3 FUNCTIONAL MODE SELECTION ........................................................................................................22 PCI/PCI-X SELECTION.............................................................................................................................22 PIN STRAPPING ........................................................................................................................................23
4 5
FORWARD AND REVERSE BRIDGING .....................................................................................................24 TRANSPARENT AND NON-TRANSPARENT BRIDGING .......................................................................25 5.1 5.2 TRANSPARENT MODE ............................................................................................................................25 NON-TRANSPARENT MODE ..................................................................................................................26
6
PCI EXPRESS FUNCTIONAL OVERVIEW ................................................................................................27 6.1 6.2 TLP STRUCTURE......................................................................................................................................27 VIRTUAL ISOCHRONOUS OPERATION ...............................................................................................28
7
CONFIGURATION REGISTERS...................................................................................................................29 7.1 CONFIGURATION REGISTER MAP.......................................................................................................29 7.2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP.................................................................34 7.3 CONTROL AND STATUS REGISTER MAP ...........................................................................................35 7.4 PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE.....................................37 7.4.1 VENDOR ID - OFFSET 00h ...............................................................................................................37 7.4.2 DEVICE ID - OFFSET 00h.................................................................................................................37 7.4.3 COMMAND REGISTER - OFFSET 04h.............................................................................................37 7.4.4 PRIMARY STATUS REGISTER - OFFSET 04h..................................................................................38 7.4.5 REVISION ID REGISTER - OFFSET 08h ..........................................................................................40 7.4.6 CLASS CODE REGISTER - OFFSET 08h..........................................................................................40 7.4.7 CACHE LINE SIZE REGISTER - OFFSET 0Ch.................................................................................40 7.4.8 PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch .................................................................40 7.4.9 HEADER TYPE REGISTER - OFFSET 0Ch ......................................................................................41 7.4.10 RESERVED REGISTERS - OFFSET 10h TO 17h ..............................................................................41 7.4.11 PRIMARY BUS NUMBER REGISTER - OFFSET 18h .......................................................................41 7.4.12 SECONDARY BUS NUMBER REGISTER - OFFSET 18h .................................................................41 7.4.13 SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h .............................................................41 7.4.14 SECONDARY LATENCY TIMER REGISTER - OFFSET 18h............................................................41 7.4.15 I/O BASE REGISTER - OFFSET 1Ch.................................................................................................41 7.4.16 I/O LIMIT REGISTER - OFFSET 1Ch................................................................................................42 Page 5 of 157
PERICOM SEMICONDUCTOR
September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.17 7.4.18 7.4.19 7.4.20 7.4.21 7.4.22 7.4.23 7.4.24 7.4.25 7.4.26 7.4.27 7.4.28 7.4.29 7.4.30 7.4.31 7.4.32 7.4.33 7.4.34 7.4.35 7.4.36 7.4.37 7.4.38 7.4.39 7.4.40 7.4.41 7.4.42 7.4.43 7.4.44 7.4.45 7.4.46 7.4.47 7.4.48 7.4.49 7.4.50 7.4.51 7.4.52 7.4.53 7.4.54 7.4.55 7.4.56 7.4.57 7.4.58 7.4.59 7.4.60 7.4.61 7.4.62 7.4.63 7.4.64 7.4.65 7.4.66 7.4.67 7.4.68 7.4.69 7.4.70
SECONDARY STATUS REGISTER - OFFSET 1Ch ...........................................................................42 MEMORY BASE REGISTER - OFFSET 20h ......................................................................................43 MEMORY LIMIT REGISTER - OFFSET 20h .....................................................................................43 PREFETCHABLE MEMORY BASE REGISTER - OFFSET 24h........................................................43 PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h.......................................................44 PREFETCHABLE BASE UPPER 32-BIT REGISTER - OFFSET 28h ...............................................44 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER - OFFSET 2Ch..............................................44 I/O BASE UPPER 16-BIT REGISTER - OFFSET 30h........................................................................44 I/O BASE UPPER 16-BIT REGISTER - OFFSET 30h........................................................................44 CAPABILITY POINTER - OFFSET 34h .............................................................................................44 EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h......................................................45 INTERRUPT LINE REGISTER - OFFSET 3Ch..................................................................................45 INTERRUPT PIN REGISTER - OFFSET 3Ch....................................................................................45 BRIDGE CONTROL REGISTER - OFFSET 3Ch ...............................................................................45 PCI DATA BUFFERING CONTROL REGISTER - OFFSET 40h......................................................46 CHIP CONTROL 0 REGISTER - OFFSET 40h..................................................................................48 RESERVED REGISTER - OFFSET 44h .............................................................................................49 ARBITER ENABLE REGISTER - OFFSET 48h..................................................................................49 ARBITER MODE REGISTER - OFFSET 48h.....................................................................................50 ARBITER PRIORITY REGISTER - OFFSET 48h ...............................................................................50 RESERVED REGISTERS - OFFSET 4Ch TO 64h..............................................................................51 EXPRESS TRANSMITTER/RECEIVER CONTROL REGISTER - OFFSET 68h................................51 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER - OFFSET 68h ......................52 RESERVED REGISTER - OFFSET 6Ch.............................................................................................52 EEPROM AUTOLOAD CONTROL/STATUS REGISTER - OFFSET 70h..........................................52 HOT SWAP CONTROL AND STATUS REGISTER - OFFSET 74h ...................................................53 GPIO DATA AND CONTROL REGISTER - OFFSET 78h.................................................................54 RESERVED REGISTER - OFFSET 7Ch.............................................................................................54 PCI-X CAPABILITY ID REGISTER - OFFSET 80h...........................................................................54 NEXT CAPABILITY POINTER REGISTER - OFFSET 80h ...............................................................54 PCI-X SECONDARY STATUS REGISTER - OFFSET 80h.................................................................54 PCI-X BRIDGE STATUS REGISTER - OFFSET 84h.........................................................................55 UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h.......................................................56 DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch................................................57 POWER MANAGEMENT ID REGISTER - OFFSET 90h...................................................................57 NEXT CAPABILITY POINTER REGISTER - OFFSET 90h ...............................................................57 POWER MANAGEMENT CAPABILITY REGISTER - OFFSET 90h .................................................57 POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h .............................58 PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER - OFFSET 94h.....................................58 RESERVED REGISTERS - OFFSET 98h TO 9Ch..............................................................................59 CAPABILITY ID REGISTER - OFFSET A0h......................................................................................59 NEXT POINTER REGISTER - OFFSET A0h .....................................................................................59 SLOT NUMBER REGISTER - OFFSET A0h ......................................................................................59 CHASSIS NUMBER REGISTER - OFFSET A0h ................................................................................59 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER - OFFSET A4h................................60 CAPABILITY ID REGISTER - OFFSET A8h......................................................................................61 NEXT POINTER REGISTER - OFFSET A8h .....................................................................................61 RESERVED REGISTER - OFFSET A8h .............................................................................................61 SUBSYSTEM VENDOR ID REGISTER - OFFSET ACh.....................................................................61 SUBSYSTEM ID REGISTER - OFFSET ACh .....................................................................................61 PCI EXPRESS CAPABILITY ID REGISTER - OFFSET B0h .............................................................61 NEXT CAPABILITY POINTER REGISTER - OFFSET B0h...............................................................62 PCI EXPRESS CAPABILITY REGISTER - OFFSET B0h ..................................................................62 DEVICE CAPABILITY REGISTER - OFFSET B4h............................................................................62 Page 6 of 157
PERICOM SEMICONDUCTOR
September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.71 7.4.72 7.4.73 7.4.74 7.4.75 7.4.76 7.4.77 7.4.78 7.4.79 7.4.80 7.4.81 7.4.82 7.4.83 7.4.84 7.4.85 7.4.86 7.4.87 7.4.88 7.4.89 7.4.90 7.4.91 7.4.92 7.4.93 7.4.94 7.4.95 7.4.96 7.4.97 7.4.98 7.4.99 7.4.100 7.4.101 7.4.102 7.4.103 7.4.104 7.4.105 7.4.106 7.4.107 7.4.108 7.4.109 7.4.110 7.4.111 7.4.112 7.4.113 7.4.114 7.4.115 7.4.116 7.4.117 7.4.118 7.4.119 7.4.120 7.4.121 7.4.122 7.4.123 7.4.124
DEVICE CONTROL REGISTER - OFFSET B8h ...............................................................................63 DEVICE STATUS REGISTER - OFFSET B8h....................................................................................64 LINK CAPABILITY REGISTER - OFFSET BCh ................................................................................65 LINK CONTROL REGISTER - OFFSET C0h ....................................................................................65 LINK STATUS REGISTER - OFFSET C0h.........................................................................................66 SLOT CAPABILITY REGISTER - OFFSET C4h ................................................................................66 SLOT CONTROL REGISTER - OFFSET C8h ....................................................................................67 SLOT STATUS REGISTER - OFFSET C8h ........................................................................................67 XPIP CONFIGURATION REGISTER 0 - OFFSET CCh ...................................................................67 XPIP CONFIGURATION REGISTER 1 - OFFSET D0h....................................................................68 XPIP CONFIGURATION REGISTER 2 - OFFSET D4h....................................................................68 HOT SWAP SWITCH DEBOUNCE COUNTER - OFFSET D4h .......................................................68 CAPABILITY ID REGISTER - OFFSET D8h .....................................................................................68 NEXT POINTER REGISTER - OFFSET D8h .....................................................................................69 VPD REGISTER - OFFSET D8h ........................................................................................................69 VPD DATA REGISTER - OFFSET DCh.............................................................................................69 RESERVED REGISTER - OFFSET E0h TO ECh................................................................................69 MESSAGE SIGNALED INTERRUPTS ID REGISTER - OFFSET F0h ..............................................69 NEXT CAPABILITIES POINTER REGISTER - OFFSET F0h ...........................................................69 MESSAGE CONTROL REGISTER - OFFSET F0h ............................................................................70 MESSAGE ADDRESS REGISTER - OFFSET F4h .............................................................................70 MESSAGE UPPER ADDRESS REGISTER - OFFSET F8h ...............................................................70 MESSAGE DATA REGISTER - OFFSET FCh ...................................................................................70 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER - OFFSET 100h .............................71 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER - OFFSET 100h .................71 NEXT CAPABILITY OFFSET REGISTER - OFFSET 100h ...............................................................71 UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 104h ..................................................71 UNCORRECTABLE ERROR MASK REGISTER - OFFSET 108h .....................................................71 UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 10Ch..............................................72 CORRECTABLE ERROR STATUS REGISTER - OFFSET 110h....................................................72 CORRECTABLE ERROR MASK REGISTER - OFFSET 114h.......................................................73 ADVANCED ERROR CAPABILITIES & CONTROL REGISTER - OFFSET 118h........................73 HEADER LOG REGISTER 1 - OFFSET 11Ch...............................................................................73 HEADER LOG REGISTER 2 - OFFSET 120h................................................................................73 HEADER LOG REGISTER 3 - OFFSET 124h................................................................................74 HEADER LOG REGISTER 4 - OFFSET 128h................................................................................74 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 12Ch......................74 SECONDARY UNCORRECTABLE ERROR MASK REGISTER - OFFSET 130h..........................75 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 134h...................75 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER - OFFSET 138h ....................76 SECONDARY HEADER LOG REGISTER - OFFSET 13Ch - 148h ..............................................76 RESERVED REGISTER - OFFSET 14Ch.......................................................................................76 VC CAPABILITY ID REGISTER - OFFSET 150h ..........................................................................76 VC CAPABILITY VERSION REGISTER - OFFSET 150h ..............................................................77 NEXT CAPABILITY OFFSET REGISTER - OFFSET 150h ...........................................................77 PORT VC CAPABILITY REGISTER 1 - OFFSET 154h .................................................................77 PORT VC CAPABILITY REGISTER 2 - OFFSET 158h .................................................................77 PORT VC CONTROL REGISTER - OFFSET 15Ch .......................................................................77 PORT VC STATUS REGISTER - OFFSET 15Ch............................................................................77 VC0 RESOURCE CAPBILITY REGISTER - OFFSET 160h...........................................................78 VC0 RESOURCE CONTROL REGISTER - OFFSET 164h............................................................78 VC0 RESOURCE STATUS REGISTER - OFFSET 168h ................................................................78 RESERVED REGISTERS - OFFSET 16Ch TO 2FCh.....................................................................78 EXTENDED GPIO DATA AND CONTROL REGISTER - OFFSET 300h .....................................78 Page 7 of 157
PERICOM SEMICONDUCTOR
September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.125 EXTRA GPI/GPO DATA AND CONTROL REGISTER - OFFSET 304h .......................................79 7.4.126 RESERVED REGISTERS - OFFSET 308h TO 30Ch......................................................................79 7.4.127 REPLAY AND ACKNOWLEDGE LATENCY TIMERS - OFFSET 310h ........................................79 7.4.128 RESERVED REGISTERS - OFFSET 314h TO FFCh .....................................................................79 7.5 PCI CONFIGURATION REGISTERS FOR NON-TRANSPARENT BRIDGE MODE...........................80 7.5.1 VENDOR ID - OFFSET 00h ...............................................................................................................80 7.5.1 DEVICE ID - OFFSET 00h.................................................................................................................80 7.5.2 PRIMARY COMMAND REGISTER - OFFSET 04h ...........................................................................80 7.5.3 PRIMARY STATUS REGISTER - OFFSET 04h..................................................................................81 7.5.4 REVISION ID REGISTER - OFFSET 08h ..........................................................................................82 7.5.5 CLASS CODE REGISTER - OFFSET 08h..........................................................................................83 7.5.6 PRIMARY CACHE LINE SIZE REGISTER - OFFSET 0Ch ...............................................................83 7.5.7 PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch .................................................................83 7.5.8 PRIMARY HEADER TYPE REGISTER - OFFSET 0Ch .....................................................................83 7.5.9 PRIMARY CSR AND MEMORY 0 BASE ADDRESS REGISTER - OFFSET 10h...............................84 7.5.10 PRIMARY CSR IO BASE ADDRESS REGISTER - OFFSET 14h.......................................................84 7.5.11 DOWNSTREAM IO OR MEMORY 1 BASE ADDRESS REGISTER - OFFSET 18h ..........................84 7.5.12 DOWNSTREAM MEMORY 2 BASE ADDRESS REGISTER - OFFSET 1Ch .....................................85 7.5.13 DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER - OFFSET 20h......................................85 7.5.14 DOWNSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER - OFFSET 24h ........................86 7.5.15 RESERVED REGISTER - OFFSET 28h .............................................................................................86 7.5.16 SUBSYSTEM ID AND SUBSYSTEM VENDOR ID REGISTER - OFFSET 2Ch ................................86 7.5.17 RESERVED REGISTER - OFFSET 30h .............................................................................................86 7.5.18 CAPABILITY POINTER - OFFSET 34h .............................................................................................86 7.5.19 EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h......................................................87 7.5.20 PRIMARY INTERRUPT LINE REGISTER - OFFSET 3Ch ................................................................87 7.5.21 PRIMARY INTERRUPT PIN REGISTER - OFFSET 3Ch ..................................................................87 7.5.22 PRIMARY MINIMUM GRANT REGISTER - OFFSET 3Ch ...............................................................87 7.5.23 PRIMARY MAXIMUM LATNECY TIMER - OFFSET 3Ch ................................................................87 7.5.24 PCI DATA BUFFERING CONTROL REGISTER - OFFSET 40h......................................................88 7.5.25 CHIP CONTROL 0 REGISTER - OFFSET 40h..................................................................................89 7.5.26 SECONDARY COMMAND REGISTER - OFFSET 44h .....................................................................90 7.5.27 SECONDARY STATUS REGISTER - OFFSET 44h............................................................................91 7.5.28 ARBITER ENABLE REGISTER - OFFSET 48h..................................................................................92 7.5.29 ARBITER MODE REGISTER - OFFSET 48h.....................................................................................93 7.5.30 ARBITER PRIORITY REGISTER - OFFSET 48h ...............................................................................94 7.5.31 SECONDARY CACHE LINE SIZE REGISTER - OFFSET 4Ch .........................................................94 7.5.32 SECONDARY LATENCY TIMER REGISTER - OFFSET 4Ch ...........................................................95 7.5.33 SECONDARY HEADER TYPE REGISTER - OFFSET 4C .................................................................95 7.5.34 SECONDARY CSR AND MEMORY 0 BASE ADDRESS REGISTER - OFFSET 50h.........................95 7.5.35 SECONDARY CSR IO BASE ADDRESS REGISTER - OFFSET 54h.................................................96 7.5.36 UPSTREAM IO OR MEMORY 1 BASE ADDRESS REGISTER - OFFSET 58h.................................96 7.5.37 UPSTREAM MEMORY 2 BASE ADDRESS REGISTER - OFFSET 5Ch ...........................................96 7.5.38 UPSTREAM MEMORY 3 BASE ADDRESS REGISTER - OFFSET 60h ............................................97 7.5.39 UPSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER - OFFSET 64h...............................97 7.5.40 EXPRESS TRANSMITTER/RECEIVER CONTROL REGISTER - OFFSET 68h................................98 7.5.41 MEMORY ADDRESS FORWARDING CONTROL REGISTER - OFFSET 68h.................................99 7.5.42 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER - OFFSET 68h ......................99 7.5.43 SUBSYSTEM VENDOR ID REGISTER - OFFSET 6Ch ...................................................................100 7.5.44 SUBSYSTEM ID REGISTER - OFFSET 6Ch....................................................................................100 7.5.45 EEPROM AUTOLOAD CONTROL/STATUS REGISTER - OFFSET 70h........................................100 7.5.46 HOT SWAP CONTROL AND STATUS REGISTER - OFFSET 74h .................................................101 7.5.47 BRIDGE CONTROL AND STATUS REGISTER - OFFSET 78h ......................................................101 7.5.48 GPIO DATA AND CONTROL REGISTER - OFFSET 78h...............................................................102 Page 8 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.49 7.5.50 7.5.51 7.5.52 7.5.53 7.5.54 7.5.55 7.5.56 7.5.57 7.5.58 7.5.59 7.5.60 7.5.61 7.5.62 7.5.63 7.5.64 7.5.65 7.5.66 7.5.67 7.5.68 7.5.69 7.5.70 7.5.71 7.5.72 7.5.73 7.5.74 7.5.75 7.5.76 7.5.77 7.5.78 7.5.79 7.5.80 7.5.81 7.5.82 7.5.83 7.5.84 7.5.85 7.5.86 7.5.87 7.5.88 7.5.89 7.5.90 7.5.91 7.5.92 7.5.93 7.5.94 7.5.95 7.5.96 7.5.97 7.5.98 7.5.99 7.5.100 7.5.101 7.5.102
SECONDARY INTERRUPT LINE REGISTER - OFFSET 7Ch ........................................................103 SECONDARY INTERRUPT PIN REGISTER - OFFSET 7Ch ..........................................................103 SECONDARY MINIMUM GRANT REGISTER - OFFSET 7Ch .......................................................103 SECONDARY MAXIMUM LATENCY TIMER - OFFSET 7Ch ........................................................103 PCI-X CAPABILITY ID REGISTER - OFFSET 80h.........................................................................103 NEXT CAPABILITY POINTER REGISTER - OFFSET 80h .............................................................103 PCI-X SECONDARY STATUS REGISTER - OFFSET 80h...............................................................104 PCI-X BRIDGE STATUS REGISTER - OFFSET 84h.......................................................................104 UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h.....................................................106 DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch..............................................106 POWER MANAGEMENT ID REGISTER - OFFSET 90h.................................................................106 NEXT CAPABILITY POINTER REGISTER - OFFSET 90h .............................................................106 POWER MANAGEMENT CAPABILITY REGISTER - OFFSET 90h ...............................................107 POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h ...........................107 PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER - OFFSET 94h...................................108 DOWNSTREAM MEMORY 0 TRANSLATED BASE REGISTER - OFFSET 98h.............................108 DOWNSTREAM MEMORY 0 SETUP REGISTER - OFFSET 9Ch ..................................................108 CAPABILITY ID REGISTER - OFFSET A0h....................................................................................109 NEXT POINTER REGISTER - OFFSET A0h ...................................................................................109 SLOT NUMBER REGISTER - OFFSET A0h ....................................................................................109 CHASSIS NUMBER REGISTER - OFFSET A0h ..............................................................................109 SECONDARY CLOCK AND CLKRUN CONTROL REGISTER - OFFSET A4h..............................109 DOWNSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER - OFFSET A8h................110 DOWNSTREAM I/O OR MEMORY 1 SETUP REGISTER - OFFSET ACh .....................................111 CAPABILITY ID REGISTER - OFFSET B0h....................................................................................111 NEXT CAPABILITY POINTER REGISTER - OFFSET B0h.............................................................111 PCI EXPRESS CAPABILITY REGISTER - OFFSET B0h ................................................................111 DEVICE CAPABILITY REGISTER - OFFSET B4h..........................................................................112 DEVICE CONTROL REGISTER - OFFSET B8h .............................................................................113 DEVICE STATUS REGISTER - OFFSET B8h..................................................................................114 LINK CAPABILITY REGISTER - OFFSET BCh ..............................................................................114 LINK CONTROL REGISTER - OFFSET C0h ..................................................................................115 LINK STATUS REGISTER - OFFSET C0h.......................................................................................115 SLOT CAPABILITY REGISTER - OFFSET C4h ..............................................................................116 SLOT CONTROL REGISTER - OFFSET C8h ..................................................................................116 SLOT STATUS REGISTER - OFFSET C8h ......................................................................................117 XPIP CONFIGURATION REGISTER 0 - OFFSET CCh .................................................................117 XPIP CONFIGURATION REGISTER 1 - OFFSET D0h..................................................................117 XPIP CONFIGURATION REGISTER 2 - OFFSET D4h..................................................................118 CAPABILITY ID REGISTER - OFFSET D8h ...................................................................................118 NEXT POINTER REGISTER - OFFSET D8h ...................................................................................118 VPD REGISTER - OFFSET D8h ......................................................................................................118 VPD DATA REGISTER - OFFSET DCh...........................................................................................118 UPSTREAM MEMORY 0 TRANSLATED BASE - OFFSET E0h.......................................................119 UPSTREAM MEMORY 0 SETUP REGISTER - OFFSET E4h .........................................................119 UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER - OFFSET E8h ......................119 UPSTREAM I/O OR MEMORY 1 SETUP REGISTER - OFFSET ECh............................................119 MESSAGE SIGNALED INTERRUPTS ID REGISTER - OFFSET F0h ............................................120 NEXT CAPABILITY POINTER REGISTER - OFFSET F0h.............................................................120 MESSAGE CONTROL REGISTER - OFFSET F0h ..........................................................................120 MESSAGE ADDRESS REGISTER - OFFSET F4h ...........................................................................121 MESSAGE UPPER ADDRESS REGISTER - OFFSET F8h .........................................................121 MESSAGE DATA REGISTER - OFFSET FCh .............................................................................121 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER - OFFSET 100h .......................121 Page 9 of 157
PERICOM SEMICONDUCTOR
September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.103 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER - OFFSET 100h ...........121 7.5.104 NEXT CAPABILITY OFFSET REGISTER - OFFSET 100h .........................................................122 7.5.105 UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 104h ............................................122 7.5.106 UNCORRECTABLE ERROR MASK REGISTER - OFFSET 108h ...............................................122 7.5.107 UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 10Ch........................................123 7.5.108 CORRECTABLE ERROR STATUS REGISTER - OFFSET 110h..................................................123 7.5.109 CORRECTABLE ERROR MASK REGISTER - OFFSET 114h.....................................................123 7.5.110 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER - OFFSET 118h.................124 7.5.111 HEADER LOG REGISTER 1 - OFFSET 11Ch.............................................................................124 7.5.112 HEADER LOG REGISTER 2 - OFFSET 120h..............................................................................124 7.5.113 HEADER LOG REGISTER 3 - OFFSET 124h..............................................................................124 7.5.114 HEADER LOG REGISTER 4 - OFFSET 128h..............................................................................124 7.5.115 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 12Ch....................125 7.5.116 SECONDARY UNCORRECTABLE ERROR MASK REGISTER - OFFSET 130h........................125 7.5.117 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 134h.................126 7.5.118 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER - OFFSET 138h ..................127 7.5.119 SECONDARY HEADER LOG REGISTER - OFFSET 13Ch - 148h ............................................127 7.5.120 RESERVED REGISTER - OFFSET 14Ch.....................................................................................127 7.5.121 VC CAPABILITY ID REGISTER - OFFSET 150h ........................................................................127 7.5.122 VC CAPABILITY VERSION REGISTER - OFFSET 150h ............................................................127 7.5.123 NEXT CAPABILITY OFFSET REGISTER - OFFSET 150h .........................................................127 7.5.124 PORT VC CAPABILITY REGISTER 1 - OFFSET 154h ...............................................................128 7.5.125 PORT VC CAPABILITY REGISTER 2 - OFFSET 158h ...............................................................128 7.5.126 PORT VC CONTROL REGISTER - OFFSET 15Ch .....................................................................128 7.5.127 PORT VC STATUS REGISTER - OFFSET 15Ch..........................................................................128 7.5.128 VC0 RESOURCE CAPBILITY REGISTER - OFFSET 160h.........................................................128 7.5.129 VC0 RESOURCE CONTROL REGISTER - OFFSET 164h..........................................................129 7.5.130 VC0 RESOURCE STATUS REGISTER - OFFSET 168h ..............................................................129 7.5.131 RESERVED REGISTERS - OFFSET 16Ch TO 2FCh...................................................................129 7.5.132 EXTENDED GPIO DATA AND CONTROL REGISTER - OFFSET 300h ...................................129 7.5.133 EXTRA GPI/GPO DATA AND CONTROL REGISTER - OFFSET 304h .....................................129 7.5.134 RESERVED REGISTERS - OFFSET 308h TO 30Ch....................................................................130 7.5.135 REPLAY AND ACKNOWLEDGE LATENCY TIMERS - OFFSET 310h ......................................130 7.5.136 RESERVED REGISTERS - OFFSET 314h TO FFCh ...................................................................130 7.6 CONTROL AND STATUS REGISTERS FOR NON-TRANSPARENT BRIDGE MODE ....................131 7.6.1 RESERVED REGISTERS - OFFSET 000h TO 004h ........................................................................131 7.6.2 DOWNSTREAM MEMORY 2 TRANSLATED BASE REGISTER - OFFSET 008h...........................131 7.6.3 DOWNSTREAM MEMORY 2 SETUP REGISTER - OFFSET 00Ch ................................................131 7.6.4 DOWNSTREAM MEMORY 3 TRANSLATED BASE REGISTER - OFFSET 010h...........................132 7.6.5 DOWNSTREAM MEMORY 3 SETUP REGISTER - OFFSET 014h .................................................132 7.6.6 DOWNSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER - OFFSET 018h .......................132 7.6.7 RESERVED REGISTERS - OFFSET 01Ch TO 030h........................................................................132 7.6.8 UPSTREAM MEMORY 3 SETUP REGISTER - OFFSET 034h .......................................................133 7.6.9 UPSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER - OFFSET 038h..............................133 7.6.10 RESERVED REGISTERS - OFFSET 3Ch TO 4Ch ...........................................................................133 7.6.11 LOOKUP TABLE OFFSET - OFFSET 50h ......................................................................................133 7.6.12 LOOKUP TABLE DATA - OFFSET 054h ........................................................................................134 7.6.13 UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER - OFFSET 058h............................134 7.6.14 UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER - OFFSET 05Ch ...........................135 7.6.15 UPSTREAM PAGE BOUNDARY IRQ 0 MASK REGISTER - OFFSET 060h...................................135 7.6.16 UPSTREAM PAGE BOUNDARY IRQ 1 MASK REGISTER - OFFSET 064h...................................135 7.6.17 RESERVED REGISTER - OFFSET 068C.........................................................................................135 7.6.18 PRIMARY CLEAR IRQ REGISTER - OFFSET 070h ........................................................................136 7.6.19 SECONDARY CLEAR IRQ REGISTER - OFFSET 070h ..................................................................136 Page 10 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.6.20 7.6.21 7.6.22 7.6.23 7.6.24 7.6.25 7.6.26 7.6.27 7.6.28 7.6.29 7.6.30 7.6.31 7.6.32 7.6.33 7.6.34 7.6.35 7.6.36 7.6.37 8 9 10 11 11.1 11.2 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 16.1 16.2 16.3 17 18
PRIMARY SET IRQ REGISTER - OFFSET 074h..............................................................................136 SECONDARY SET IRQ REGISTER - OFFSET 074h........................................................................136 PRIMARY CLEAR IRQ MASK REGISTER - OFFSET 078h.............................................................137 SECONDARY CLEAR IRQ MASK REGISTER - OFFSET 078h .......................................................137 PRIMARY SET IRQ MASK REGISTER - OFFSET 07Ch..................................................................137 SECONDARY SET IRQ MASK REGISTER - OFFSET 07Ch............................................................137 RESERVED REGISTERS - OFFSET 080h TO 09Ch........................................................................138 SCRATCHPAD 0 REGISTER - OFFSET 0A0h .................................................................................138 SCRATCHPAD 1 REGISTER - OFFSET 0A4h .................................................................................138 SCRATCHPAD 2 REGISTER - OFFSET 0A8h .................................................................................138 SCRATCHPAD 3 REGISTER - OFFSET 0ACh.................................................................................138 SCRATCHPAD 4 REGISTER - OFFSET 0B0h .................................................................................139 SCRATCHPAD 5 REGISTER - OFFSET 0B4h .................................................................................139 SCRATCHPAD 6 REGISTER - OFFSET 0B8h .................................................................................139 SCRATCHPAD 7 REGISTER - OFFSET 0BCh.................................................................................139 RESERVED REGISTERS - OFFSET 0C0h TO 0FCh.......................................................................139 LOOKUP TABLE REGISTERS - OFFSET 100h TO 1FCh ..............................................................140 RESERVED REGISTERS - OFFSET 200h TO FFCh .......................................................................140
GPIO PINS AND SM BUS ADDRESS ..........................................................................................................141 CLOCK SCHEME ..........................................................................................................................................142 INTERRUPTS .............................................................................................................................................142 EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS.................................................144 EEPROM (I2C) INTERFACE...................................................................................................................144 SYSTEM MANAGEMENT BUS .............................................................................................................144 HOT PLUG OPERATION .........................................................................................................................144 RESET SCHEME........................................................................................................................................145 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER.............................................................................146 INSTRUCTION REGISTER.....................................................................................................................146 BYPASS REGISTER ................................................................................................................................146 DEVICE ID REGISTER ...........................................................................................................................146 BOUNDARY SCAN REGISTER .............................................................................................................147 JTAG BOUNDARY SCAN REGISTER ORDER....................................................................................147 POWER MANAGEMENT .........................................................................................................................152 ELECTRICAL AND TIMING SPECIFICATIONS ................................................................................153 ABSOLUTE MAXIMUM RATINGS.......................................................................................................153 DC SPECIFICATIONS .............................................................................................................................153 AC SPECIFICATIONS .............................................................................................................................154 PACKAGE INFORMATION.....................................................................................................................155 ORDERING INFORMATION...................................................................................................................157
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LIST OF TABLES
TABLE 14-1 JTAG BOUNDARY SCAN REGISTER DEFINITION ....................................................................................147 TABLE 16-1 ABSOLUTE MAXIMUM RATINGS .............................................................................................................153 TABLE 16-2 DC ELECTRICAL CHARACTERISTICS.......................................................................................................153 TABLE 16-3 PCI BUS TIMING PARAMETERS ..............................................................................................................154
LIST OF FIGURES
FIGURE 1-1 PI7C9X130 TOPOLOGY ............................................................................................................................13 FIGURE 2-1 PIN ASSIGNMENTS.....................................................................................................................................20 FIGURE 3-1 FUNCTIONAL MODE SELECTION ................................................................................................................22 FIGURE 3-2 PCI / PCI-X SELECTION...........................................................................................................................23 FIGURE 3-3 PIN STRAPPING .........................................................................................................................................23 FIGURE 4-1 FORWARD AND NON-TRANSPARENT MODE..............................................................................................24 FIGURE 4-2 REVERSE AND TRANSPARENT MODE........................................................................................................25 FIGURE 5-1 NON-TRANSPARENT REGISTERS...............................................................................................................27 FIGURE 6-1 TLP FORMAT ...........................................................................................................................................27 FIGURE 7-1 CONFIGURATION REGISTER MAP (00H - FFH) .........................................................................................29 FIGURE 7-2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP (100H - FFFH) ....................................................34 FIGURE 7-3 CONTROL AND STATUS REGISTER (CSR) MAP (000H - FFFH) ................................................................35 FIGURE 8-1 SM BUS DEVICE ID STRAPPING..............................................................................................................141 FIGURE 10-1 PCIE INTERRUPT MESSAGES TO PCI INTERRUPTS MAPPING IN REVERSE BRIDGE MODE .....................143 FIGURE 10-2 PCI INTERRUPTS TO PCIE INTERRUPT MESSAGES MAPPING IN FORWARD BRIDGE MODE....................143 FIGURE 14-1 INSTRUCTION REGISTER CODES ............................................................................................................146 FIGURE 14-2 JTAG DEVICE ID REGISTER .................................................................................................................147 FIGURE 16-1 PCI SIGNAL TIMING CONDITIONS .........................................................................................................155 FIGURE 17-1 TOP VIEW DRAWING .............................................................................................................................155 FIGURE 17-2 BOTTOM VIEW DRAWING......................................................................................................................156 FIGURE 17-3 PACKAGE OUTLINE DRAWING...............................................................................................................157
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1
INTRODUCTION
PI7C9X130 is a PCIe-to-PCI/PCI-X bridge. PI7C9X130 is compliant with the PCI Express Base Specification, Revision 1.1, the PCI Express Card Electromechnical Specification, Revision 1.1, the PCI Local Bus Specification, Revision 3.0 and PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. PI7C9X130 supports transparent and non-transparent mode of operations. Also, PI7C9X130 supports forward and reverse bridging. In forward bridge mode, PI7C9X130 has an x4 PCI Express upstream port and a 64-bit PCI/PCI-X downstream port. The 64-bit PCI-X downstream port is 133MHz capable (see Figure 1-1). In reverse bridge mode, PI7C9X130 has a 64-bit PCI-X upstream port and an x4 PCI Express downstream port. PI7C9X130 configuration registers are backward compatible with existing PCI bridge software and firmware. No modification of PCI bridge software and firmware is needed for the original operation. Figure 1-1 PI7C9X130 Topology
Rx
Tx
X4 PCI Express Link
PCI-X 64-bit, 133MHz Bus
1.1
PCI EXPRESS FEATURES
* * * * * * * * * * * * Compliant with PCI Express Base Specification, Revision 1.1 Compliant with PCI Express Card Electromechnical Specification, Revision 1.1 Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 Physical Layer interface (x4 link with 2.5Gb/s data rate) Lane polarity toggle Virtual isochronous support (upstream TC1-7 generation, downstream TC1-7 mapping) ASPM support Beacon support CRC (16-bit), LCRC (32-bit) ECRC and advanced error reporting PRBS (Pseudo Random Bit Sequencing) generator/checker for chip testing Maximum payload size to 512 bytes Page 13 of 157
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1.2
PCI/PCI-X FEATURES
* * * * * * * * * * * * Compliant with PCI Local Bus Specification, Revision 3.0 Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.2 Compliant with PCI Bus PM Interface Specification, Revision 1.1 Compliant with PCI Hot-Plug Specification, Revision 1.1 Compliant with PCI Mobile Design Guide, Version 1.1 Compliant with PCI-X Protocol Addendum to the PCI Local Bus Specification, Revision 2.0a PME support 3.3V PCI signaling with 5V I/O tolerance Provides two level arbitration support for six PCI Bus masters 16-bit address decode for VGA Subsystem Vendor and Subsystem Device IDs support PCI INT interrupt or MSI Function support
1.3
GENERAL FEATURES
* * * * * * * * * * * * * Compliant with Advanced Configuration and Power Interface Specification (ACPI), Revision 2.0b Compliant with System Management (SM) Bus, Version 2.0 Forward bridging (PCI Express as primary bus, PCI as secondary bus) Reverse bridging (PCI as primary bus, PCI Express as secondary bus) Transparent mode support Non-transparent mode Support GPIO support (4 bi-directional pins) Power Management (including ACPI, CLKRUN_L, PCI_PM) Masquerade Mode (pre-loadable vendor, device, and revision IDs) EEPROM (I2C) Interface SM Bus Interface Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support Power consumption at about 1.5 Watt in typical condition
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2
2.1
PIN DEFINITION
SIGNAL TYPES
TYPE OF SIGNAL B I IU ID IOD OD O P G DESCRIPTION Bi-directional Input Input with pull-up Input with pull-down Bi-directional with open drain output Open drain output Output Power Ground
"_L" in signal name indicates Active LOW signal
2.2
PCI EXPRESS SIGNALS
NAME REFCLKP REFCLKN RAP RAN RBP RBN RCP RCN RDP RDN TAP TAN TBP TBN TCP TCN TDP TDN RREF PIN ASSIGNMENT D2, D1 F2, F1 H2, H1 K2, K1 M2, M1 E4, E3 G4, G3 J4, J3 L4, L3 H4 TYPE I I I I I O O O O I DESCRIPTION Reference Clock Input s: Connect to external 100MHz differential clock. PCI Express data input s: Differential data receiver input signals for lane A PCI Express data input s: Differential data receiver input signals for lane B PCI Express data input s: Differential data receiver input signals for lane C PCI Express data input s: Differential data receiver input signals for lane D PCI Express data outputs: Differential data transmitter output signals for lane A PCI Express data outputs: Differential data transmitter output signals for lane B PCI Express data outputs: Differential data transmitter output signals for lane C PCI Express data outputs: Differential data transmitter output signals for lane D Resistor Reference: It is used to connect an external resistor (2.4K Ohm +/- 1%) to VSS to provide a reference current for the driver and equalization circuit. PCI Express Fundamental Reset: PI7C9X130 uses this reset to initialize the internal state machines.
PERST_L
P1
I
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2.3
PCI SIGNALS
NAME AD [31:0] PIN ASSIGNMENT D5, A6, B6, C6, D6, A7, B7, C7, A8, B8, C8, D8, A9, B9, C9, D9, G16, G15, G14, G13, H16, H15, H14, H13, J15, J14, J13, K16, K15, K14, K13, L16 N11, P11, R11, T11, N12, P12, R12, T12, R13, T13, P14, R14, T14, T15, R15, R16, D16, C15, C16, B16, B15, A15, C14, B14, C13, B13, A13, D12, C12, B12, A12, D11 D7, A10, F13, J16 TYPE B DESCRIPTION Address / Data: Multiplexed address and data bus. Address phase is aligned with first clock of FRAME_L assertion. Data phase is aligned with IRDY_L or TRDY_L assertion. Data is transferred on rising edges of FBCLKIN when both IRDY_L and TRDY_L are asserted. During bus idle (both FRAME_L and IRDY_L are de-asserted), PI7C9X130 drives AD [31:0] to a valid logic level when arbiter is parking to PI7C9X130 on PCI bus.
AD [63:32]
B
Upper 32-bit Address / Data: Multiplexed address and data bus. Address phase is aligned with first clock of FRAME_L assertion. Data phase is aligned with IRDY_L or TRDY_L assertion. Data is transferred on rising edges of FBCLKIN when both IRDY_L and TRDY_L are asserted. During bus idle (both FRAME_L and IRDY_L are deasserted), PI7C9X130 drives AD [63:32] to a valid logic level when arbiter is parking to PI7C9X130 on PCI bus.
CBE [3:0]
B
CBE [7:4]
P13, P15, A14, C11
B
PAR
F14
B
PAR64
D15
B
Command / Byte Enables (Active LOW): Multiplexed command at address phase and byte enable at data phase. During address phase, the initiator drives commands on CBE [3:0] signals to start the transaction. If the command is a write transaction, the initiator will drive the byte enables during data phase. Otherwise, the target will drive the byte enables during data phase. During bus idle, PI7C9X130 drives CBE [3:0] signals to a valid logic level when arbiter is parking to PI7C9X130 on PCI bus. Upper 4-bit Command / Byte Enables (Active LOW): Multiplexed command at address phase and byte enable at data phase. During address phase, the initiator drives commands on CBE [3:0] signals to start the transaction. If the command is a write transaction, the initiator will drive the byte enables during data phase. Otherwise, the target will drive the byte enables during data phase. During bus idle, PI7C9X130 drives CBE [7:4] signals to a valid logic level when arbiter is parking to PI7C9X130 on PCI bus. Parity Bit: Parity bit is an even parity (i.e. even number of 1's), which generates based on the values of AD [31:0], CBE [3:0]. If PI7C9X130 is an initiator with a write transaction, PI7C9X130 will tri-state PAR. If PI7C9X130 is a target and a write transaction, PI7C9X130 will drive PAR one clock after the address or data phase. If PI7C9X130 is a target and a read transaction, PI7C9X130 will drive PAR one clock after the address phase and tri-state PAR during data phases. PAR is tri-stated one cycle after the AD lines are tri-stated. During bus idle, PI7C9X130 drives PAR to a valid logic level when arbiter is parking to PI7C9X130 on PCI bus. Parity Bit for Upper 32-bit: Parity bit is an even parity (i.e. even number of 1's), which generates based on the values of AD [63:32], CBE [7:4]. If PI7C9X130 is an initiator with a write transaction, PI7C9X130 will tri-state PAR64. If PI7C9X130 is a target and a write transaction, PI7C9X130 will drive PAR64 one clock after the address or data phase. If PI7C9X130 is a target and a read transaction, PI7C9X130 will drive PAR64 one clock after the address phase and tri-state PAR64 during data phases. PAR64 is tri-stated one cycle after the AD lines are tri-stated. During bus idle, PI7C9X130 drives PAR64 to a valid logic level when arbiter is parking to PI7C9X130 on PCI bus.
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NAME FRAME_L
PIN ASSIGNMENT B10
TYPE B
DESCRIPTION FRAME (Active LOW): Driven by the initiator of a transaction to indicate the beginning and duration an access. The de-assertion of FRAME_L indicates the final data phase signaled by the initiator in burst transfers. Before being tri-stated, it is driven to a de-asserted state for one cycle. IRDY (Active LOW): Driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. TRDY (Active LOW): Driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. Once asserted in a data phase, it is not de-asserted until the end of the data phase. Before tri-stated, it is driven to a de-asserted state for one cycle. Device Select (Active LOW): Asserted by the target indicating that the device is accepting the transaction. As a master, PI7C9X130 waits for the assertion of this signal within 5 cycles of FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, it is driven to a de-asserted state for one cycle. STOP (Active LOW): Asserted by the target indicating that the target is requesting the initiator to stop the current transaction. Before tristated, it is driven to a de-asserted state for one cycle. LOCK (Active LOW): Asserted by the initiator for multiple transactions to complete. PI7C9X130 does not support any upstream LOCK transaction. Initialization Device Select: Used as a chip select line for Type 0 configuration access to bridge's configuration space. Parity Error (Active LOW): Asserted when a data parity error is detected for data received on the PCI bus interface. Before being tristated, it is driven to a de-asserted state for one cycle. System Error (Active LOW): Can be driven LOW by any device to indicate a system error condition. If SERR control is enabled, PI7C9X130 will drive this pin on: Address parity error Posted write data parity error on target bus Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout Errors reported from PCI Express port (advanced error reporting) in transparent mode. This signal is an open drain buffer that requires an external pull-up resistor for proper operation. Request (Active LOW): REQ_Ls are asserted by bus master devices to request for transactions on the PCI bus. The master devices de-assert REQ_Ls for at least 2 PCI clock cycles before asserting them again. If external arbiter is selected (CFN_L=1), REQ_L [0] will be the bus grant input to PI7C9X130. Also, REQ_L [5:2] will become the GPI [3:0]. Grant (Active LOW): PI7C9X130 asserts GNT_Ls to release PCI bus control to bus master devices. During idle and all GNT_Ls are deasserted and arbiter is parking to PI7C9X130, PI7C9X130 will drive AD, CBE, and PAR to valid logic levels. If external arbiter is selected (CFN_L=1), GNT_L [0] will be the bus request from PI7C9X130 to external arbiter. Also, GNT_L [5:2] will become the GPO [3:0]. Request for 64-bit transfer (Active LOW): PI7C9X130 asserts REQ64_L to request for 64-bit transactions on the PCI bus when PI7C9X130 is the bus master. REQ64_L is an input when PI7C9X130 is a target device. Acknowledge for 64-bit transfer (Active LOW): When PI7C9X130 is a target device and drives ACK64_L to signal the bus master to use 64bit transfer. When PI7C9X130 is the bus master, ACK64_L is an input.
IRDY_L
C10
B
TRDY_L
D10
B
DEVSEL_L
A11
B
STOP_L
B11
B
LOCK_L
E13
B
IDSEL PERR_L
M13 F16
I B
SERR_L
F15
IOD
REQ_L [5:0]
P3, N3, T2, R2, P2, R1
I
GNT_L [5:0]
T5, R5, P5, N5, T4, R4
O
REQ64_L
D14
B
ACK64_L
E16
B
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PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
NAME CLKOUT [6:0] RESET_L INTA_L INTB_L INTC_L INTD_L FBCLKIN
PIN ASSIGNMENT N10, T9, R9, P9, N9, T8, R8 N7 P4 R6 T10 N15 B4
TYPE O B IOD
DESCRIPTION PCI Clock Outputs: PCI clock outputs are derived from the CLKIN and provide clocking signals to external PCI Devices. RESET_L (Active LOW): When RESET_L active, all PCI signals should be asynchronously tri-stated. Interrupt: Signals are asserted to request an interrupt. After asserted, it can be cleared by the device driver. INTA_L, INTB_L, INTC_L, INTD_L signals are inputs and asynchronous to the clock in the forward mode. In reverse mode, INTA_L, INTB_L, INTC_L, and INTD_L are open drain buffers for sending interrupts to the host interrupt controller. Feedback Clock Input: It connects to one of the CLKOUT [6:0] Output Signals and provides internal clocking to PI7C9X130 PCI bus interface. PCI Clock Input: PCI Clock Input Signal connects to an external clock source. The PCI Clock Outputs CLKOUT [6:0] pins are derived from CLKIN Input. M66EN Input: It is driven high or low to enable the internal clock generator to provide clock outputs to CLKOUT[6:0] pins.
I
CLKIN / M66EN
T6
I
2.4
MODE SELECT AND STRAPPING SIGNALS
NAME TM2 PIN ASSIGNMENT P16 TYPE I DESCRIPTION Mode Select 2: TM2 is a strapping pin. When TM2 is strapped low for normal operations and strapped high for testing functions. See table 3-1 for mode selection and 3-2 for strapping control for details. Mode Select 1: Mode Selection Pin to select EEPROM or SM Bus. TM1=0 for EEPROM (I2C) support and TM1=1 for SM Bus support. TM1 is also a strapping pin. See table 3-1 mode selection and 3-2 for strapping control. Mode Select 0: Mode Selection Pin to select transparent or nontransparent mode. TM0=0 for transparent bridge function mode and TM0=1 for non-transparent bridge function mode. TM0 is also a strapping pin. See table 3-1 for mode selection and 3-2 for strapping control. Mask Input for CLKOUT: MSK_IN is used by PI7C9X130 to enable or disable the clock outputs. MSK_IN is also a strapping pin. When it is strapped to high, hot-plug is enabled. See table 3-2 for strapping control. Forward or Reverse Bridging Pin: REVRSB pin controls the Forward (REVRSB=0) or Reverse (REVRSB=1) Bridge Mode of PI7C9X130. This pin is also a strapping pin. See table 3-1 for mode selection. Bus Central Function Control Pin (Active Low): To enable the internal arbiter, CFN_L pin should be tied low. When it's tied high, an external arbiter is required to arbitrate the bus. In external arbiter mode, REQ_L [0] is re-configured to be the secondary bus grant input, and GNT_L [0] is reconfigured to be the secondary bus request output. Also, REQ_L [5:2] and GNT_L [5:2] become GPI [3:0] and GPO [3:0] respectively if external arbiter is selected. CFN_L has a weak internal pull-down resistor. See table 3-1 for mode selection.
TM1
A3
I
TM0
A2
I
MSK_IN
N16
I
REVRSB
N14
I
CFN_L
P7
ID
2.5
JTAG BOUNDARY SCAN SIGNALS
NAME TCK PIN ASSIGNMENT L13 TYPE IU DESCRIPTION Test Clock: TCK is the test clock to synchronize the state information and data on the PCI bus side of PI7C9X130 during boundary scan operation.
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NAME TMS TDO TDI
PIN ASSIGNMENT M16 M14 M15
TYPE IU O IU
DESCRIPTION Test Mode Select: TMS controls the state of the Test Access Port (TAP) controller. Test Data Output: TDO is the test data output and connects to the end of the JTAG scan chain. Test Data Input: TDI is the test data input and connects to the beginning of the JTAG scan chain. It allows the test instructions and data to be serially shifted into the PCI side of PI7C9X130. Test Reset (Active LOW): TRST_L is the test reset to initialize the Test Access Port (TAP) controller.
TRST_L
L14
IU
2.6
MISCELLANEOUS SIGNALS
NAME GPIO [6:0] PIN ASSIGNMENT L15, R10, P10, R7, T7, N8, P8 TYPE B DESCRIPTION General Purpose I/O Data Pins: The 7 general-purpose signals are programmable as either input-only or bi-directional signals by writing the GPIO output enable control register in the configuration space. See chapter 8 for more information. SMBUS / EEPROM Clock Pin: When EEPROM (I2C) interface is selected (TM1=0), this pin is an output of SCL clock and connected to EEPROM clock input. When SMBUS interface is selected (TM1=1), this pin is an input for the clock of SMBUS. SMBUS / EEPROM Data Pin: Data Interface Pin to EERPOM or SMBUS. When EEPROM (I2C) interface is selected (TM1=0), this pin is a bi-directional signal. When SMBUS interface is selected (TM1=1), this pin is an open drain signal. Power Management Event Pin: Power Management Event Signal is asserted to request a change in the device or link power state. Clock Run Pin (Active LOW): The Clock Run signal, for mobile environment, is asserted and de-asserted to indicate the status of the PCI Clock. PCI-X Capability Pin: PI7C9X130 can be forced to PCI mode if PCIXCAP is tied to ground with a capacitor (0.1uF) in parallel. If PCIXCAP is connected to ground through a capacitor (0.1uF), PI7C9X110 will be in 133MHz PCI-X mode. If PCIXCAP is connected to ground through a resistor (10K Ohm) with a capacitor (0.1uF) in parallel, PI7C9X110 will be in 66MHz PCI-X mode. PCIXCAP Pull-up driver: PI7C9X130 drives this pin for PCI-X mode detection. Control 64-bit bus width: PI7C9X130 operates with 64-bit bus when DEV64=1. When DEV64=0, PI7C9X130 operates with 32-bit bus. Select 100MHz frequency: When SEL100=1, PI7C9X110 expects to run at 100MHz clock. When SEL100=0, PI7C9X130 expects to run at 133MHz.. Hot Swap Enable: PI7C9X130 supports hot swap when HSEN is set to high. Tie LOW if hot swap function is not used. Hot Swap Switch: PI7C9X130 detects HSSW input to monitor the insertion or impending extraction of a board. LED On/Off: PI7C9X130 drives LOO for LED illumination that signals the operator to extract the board. ENUM_L signal: PI7C9X130 drives ENUM_L to notify the system host that either a board has been freshly inserted or is about to be extracted.
SMBCLK / SCL
B5
B
SMBDAT / SDA
A5
B/IOD
PME_L CLKRUN_L
C5 C4
B B
PCIXCAP
A4
I
PCIXUP DEV64 SEL100
B3 E15 E14
O I I
HSEN HSSW LOO ENUM_L
R3 T3 N6 P6
I I O OD
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2.7
POWER AND GROUND PINS
NAME VDDA VDDP VDDAUX VTT VDDA_PLL VDDP_PLL VDDC PIN ASSIGNMENT E2, J1, J2, H3 G2, F3, J5, M3, N2 F4, L1 G1, L5 D3 C2 M5, M6, M11, M12, J11, H11, E11, E10, K5, A1 H5 T1, N4, M7, M8, M9, L10, L11, M10, T16, N13, L12, K12, K11, J12, H12, G11, G12, F12, A16, D13, E12, F11, E9, E8, E7, E6, E5 B2 B1, C1, C3, D4, F5, E1, G5, K3, K4, L2, N1, M4, L6, K6, L7, K7, L8, L9, K8, K9, K10, J6, J7, J8, J9, J10, H8, H9, H10, G10, F10, F9, F8, F7, F6, G9, G8, G7, G6, H7, H6 TYPE P P P P P P P DESCRIPTION Analog Voltage Supply for PCI Express Interface: Connect to the 1.8V Power Supply. Digital Voltage Supply for PCI Express Interface: Connect to the 1.8V Power Supply. Auxiliary Voltage Supply for PCI Express Interface: Connect to the 1.8V Power Supply. Termination Supply Voltage for PCI Express Interface: Connect to the 1.8V Power Supply. Analog Voltage Supply for PLL at PCI Interface: Connect to the 1.8V Power Supply. Digital Voltage Supply for PLL at PCI Interface: Connect to the 1.8V Power Supply. Core Supply Voltage: Connect to the 1.8V Power Supply.
VDDCAUX VD33
P P
Auxiliary Core Supply Voltage: Connect to the 1.8V Power Supply. I/O Supply Voltage for PCI Interface: Connect to the 3.3V Power Supply for PCI I/O Buffers.
VAUX VSS
P P
Auxiliary I/O Supply Voltage for PCI interface: Connect to the 3.3V Power Supply. Ground: Connect to Ground.
2.8
PIN ASSIGNMENT
Figure 2-1 Pin Assignments
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 Name VDDC TM0 TM1 PCIXCAP SMBDAT / SDA AD[30] AD[26] AD[23] AD[19] CBE[2] DEVSEL_L AD[33] Pin E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 Name VSS VDDA TAN TAP VD33 VD33 VD33 VD33 VD33 VDDC VDDC VD33 Pin J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 Name VDDA VDDA TCN TCP VDDP VSS VSS VSS VSS VSS VDDC VD33 Pin N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 Name VSS VDDP REQ_L[4] / GPI[2] VD33 GNT_L[2] / GPO[0] LOO RESET_L GPIO[1] CLKOUT[2] CLKOUT[6] AD[63] AD[59]
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Pin A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16
Name AD[37] CBE[5] AD[42] VD33 VSS VAUX PCIXUP FBCLKIN SMBCLK / SCL AD[29] AD[25] AD[22] AD[18] FRAME_L STOP_L AD[34] AD[38] AD[40] AD[43] AD[44] VSS VDDP_PLL VSS CLKRUN_L PME_L AD[28] AD[24] AD[21] AD[17] IRDY_L CBE[4] AD[35] AD[39] AD[41] AD[46] AD[45] REFCLKN REFCLKP VDDA_PLL VSS AD[31] AD[27] CBE[3] AD[20] AD[16] TRDY_L AD[32] AD[36] VD33 REQ64_L PAR64 AD[47]
Pin E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16
Name LOCK_L SEL100 DEV64 ACK64_L RAN RAP VDDP VDDAUX VSS VSS VSS VSS VSS VSS VD33 VD33 CBE[1] PAR SERR_L PERR_L VTT VDDP TBN TBP VSS VSS VSS VSS VSS VSS VD33 VD33 AD[12] AD[13] AD[14] AD[15] RBN RBP VDDA RREF VDDCAUX VSS VSS VSS VSS VSS VDDC VD33 AD[8] AD[9] AD[10] AD[11]
Pin J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16
Name AD[5] AD[6] AD[7] CBE[0] RCN RCP VSS VSS VDDC VSS VSS VSS VSS VSS VD33 VD33 AD[1] AD[2] AD[3] AD[4] VDDAUX VSS TDN TDP VTT VSS VSS VSS VSS VD33 VD33 VD33 TCK TRST_L GPIO[6] AD[0] RDN RDP VDDP VSS VDDC VDDC VD33 VD33 VD33 VD33 VDDC VDDC IDSEL TDO TDI TMS
Pin N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16
Name VD33 REVRSB INTD_L MSK_IN PERST_L REQ_L[1] REQ_L[5] / GPI[3] INTA_L GNT_L[3] / GPO[1] ENUM_L CFN_L GPIO[0] CLKOUT[3] GPIO[4] AD[62] AD[58] CBE[7] AD[53] CBE[6] TM2 REQ_L[0] REQ_L[2] / GPI[0] HSEN GNT_L[0] GNT_L[4] / GPO[2] INTB_L GPIO[3] CLKOUT[0] CLKOUT[4] GPIO[5] AD[61] AD[57] AD[55] AD[52] AD[49] AD[48] VD33 REQ_L[3] / GPI[1] HSSW GNT_L[1] GNT_L[5] / GPO[3] CLKIN / M66EN GPIO[2] CLKOUT[1] CLKOUT[5] INTC_L AD[60] AD[56] AD[54] AD[51] AD[50] VD33
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3
3.1
MODE SELECTION AND PIN STRAPPING
FUNCTIONAL MODE SELECTION
If TM2 is strapped to low, PI7C9X130 uses TM1, TM0, CFN_L, and REVRSB pins to select different modes of operations. These four input signals are required to be stable during normal operation. One of the sixteen combinations of normal operation can be selected by setting the logic values for the four mode select pins. For example, if the logic values are low for all four (TM1, TM0, CFN_L, and REVRSB) pins, the normal operation will have EEPROM (I2C) support in transparent mode with internal arbiter in forward bridge mode. The designated operation with respect to the values of the TM1, TM0, CFN_L, and REVRSB pins are defined on Table 3-1: Figure 3-1 Functional Mode Selection
TM2 Strapped
0 0 0 0 0 0 0 0
TM1
0 1 X X X X X X
TM0
X X 0 1 X X X X
CFN_L
X X X X 0 1 X X
REVRSB
X X X X X X 0 1
Functional Mode
EEPROM (I2C) support SM Bus support Transparent mode Non-Transparent mode Internal arbiter External arbiter Forward bridge mode Reverse bridge mode
3.2
PCI/PCI-X SELECTION
The secondary interface is capable of operating in either conventional PCI mode or in PCI-X mode. PI7C9X130 controls the mode and frequency for the secondary bus by utilizing a pull-up circuit connected to PCIXCAP. There are two pull-up resistors in the circuit as recommended by the PCI-X addendum. The first resistor is a weak pull-up (56K ohms) whose value is selected to set the voltage of PCIXCAP below its low threshold when a PCI-X 66MHz device is attached to the secondary bus. The second resistor is a strong pull-up, externally wired between PCIXCAP and PCIXUP. The value of the resistor (1K ohm) is selected to set the voltage of PCIXCAP above its high threshold when all devices on the secondary are PCI-X 66MHz capable. To detect the mode and frequency of the secondary bus, PCIXUP is initially disabled and PI7C9X130 samples the value on PCIXCAP. If PI7C9X130 sees logic LOW on PCIXCAP, one or more devices on the secondary have either pulled the signal to ground (PCI-X 66MHz capable) or tied it to ground (only capable of conventional PCI mode). To differentiate between the two conditions, PI7C9X130 then enables PCIXUP to put the strong pull-up into the circuit node. If PCIXCAP remains at logic LOW, it must be tied to ground by one or more devices, and the bus is initialized to conventional PCI mode. If PCIXUP can be pulled up, one or more devices are capable of only PCI-X 66MHz operation so the bus is initialized to PCI-X 66MHz mode. If PI7C9X130 sees logic HIGH on PCIXCAP, then all devices on the secondary bus are capable of PCI-X 100MHz or 133MHz operation. PI7C9X130 then samples SEL100 to distinguish between the 100MHz and 133MHz clock frequencies. If PI7C9X130 sees logic HIGH on SEL100, the secondary bus is initialized to PCI-X 100MHz mode. If the value is LOW, PCI-X 133MHz is initialized. These two clock frequencies allow the flexibility to support different bus loading conditions.
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There is no pin for M66EN for the secondary interface of PI7C9X130 because the internal PLL is bypassed in conventional PCI mode. CLKIN is used directly, eliminating the need to distinguish between conventional PCI 33MHz and 66MHz. Figure 3-2 PCI / PCI-X Selection
PI7C9X130
3.3v 56 K Ohms PCIXCAP 1K Ohms Strong Pull-up 0.01uF PCIXUP 10K Ohms 0.01uF 0.01uF Weak Pull-up
Enable During Bus Capability Determination
3.3v
PCI Card 3.3v 10 K Ohms SEL100 Low for 133 MHz High for 100 MHz
PCI-X 66MHz Card
PCI-X 100MHz or 133MHz Card
3.3
PIN STRAPPING
If TM2 is strapped to high, PI7C9X130 uses TM1, TM0, and MSK_IN as strapping pins. The strapping functions are listed in Table 3-2 to show the states of operations during the PCI Express PERST_L deassertion transition in forward bridge mode or PCI RESET_L de-assertion transition in reverse bridge mode. Figure 3-3 Pin Strapping
TM2 Strapped
1 1 1 1
TM1 Strapped
0 0 1 1
TM0 Strapped
0 1 0 1
MSK_IN Strapped
1 1 1 1
Test Functions
PLL test Shorten initialization test with Hot-Plug enabled Functional loopback test Bridge test (PRBS, IDDQ, etc.)
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TM2 Strapped
1 1 1 1
TM1 Strapped
0 0 1 1
TM0 Strapped
0 1 0 1
MSK_IN Strapped
0 0 0 0
Test Functions
Reserved Shorten initialization test with Hot-Plug disabled Reserved Reserved
4
FORWARD AND REVERSE BRIDGING
PI7C9X130 supports forward or reverse and transparent or non-transparent combination modes of operation. For example, when PI7C9X130 is operating in forward (REVRSB=0) and non-transparent bridge mode (TM0=1) shown in Figure 4-1, its PCI Express interface is connected to a root complex and its PCI-X bus interface is connected to PCI-X devices. Another example, PI7C9X130 can be configured as a reverse (REVRSB=1) and transparent (TM0=0) bridge shown in Figure 4-2. The non-transparent bridge feature of PI7C9X130 allows the I/O Processor to be isolated from the Host Processor and its memory map which avoiding memory address conflict when both host and I/O processors are needed side-by-side. PCI/PCI-X based systems and peripherals are ubiquitous in the I/O interconnect technology market today. It will be a tremendous effort to convert existing PCI/PCI-X based products to be used in PCI Express systems. PI7C9X130 provides a solution to bridge existing PCI/PCI-X based products to the latest PCI Express technology. Figure 4-1 Forward and Non-transparent Mode
Host Processor
System Memory
Root Complex
Other PCI Express Subsystems
X4 Link
I/O Processor
PCI-X 64-bit, 133MHz
Gigabit Ethernet
Local Memory
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In reverse (REVRSB=1) and transparent (TM0=0) mode shown in Figure 3-2, PI7C9X130 becomes a PCI-to-PCI Express bridge that its PCI-X bus interface is connected to the host chipset between and the PCI Express x4 link. It enables the legacy PCI/PCI-X Host Systems to provide PCI Express capability. PI7C9X130 provides a solution to convert existing PCI/PCI-X based designs to adapt quickly into PCI Express base platforms. Existing PIC/PCI-X based applications will not have to undergo a complete rearchitecture in order to interface to PCI Express technology. Figure 4-2 Reverse and Transparent Mode
Host Processor
System Memory
Chipset
PCI-X 64-bit, 133 MHz
Gigabit Ethernet
X4 link
5
5.1
TRANSPARENT AND NON-TRANSPARENT BRIDGING
TRANSPARENT MODE
In transparent bridge mode, base class code of PI7C9X130 is set to be 06h (bridge device). The subclass code is set to be 04h (PCI-to-PCI bridge). Programming interface is 00h. Hence, PI7C9X130 is not a subtractive decoding bridge. PI7C9X130 has type-1 configuration header if TM0 is set to 0 (transparent bridge mode). These configuration registers are the same as traditional transparent PCI-to-PCI Bridge. In fact, it is backward compatible to the software that supporting traditional transparent PCI-to-PCI bridges. Configuration registers can be accessed from several different ways. For PCI Express access, PCI Express configuration transaction is in forward bridge mode. For PCI access, PCI configuration cycle is mainly in reverse bridge mode. However, PI7C9X130 allows PCI configuration access in forward mode as secondary bus configuration access. For I2C access, I2C bus protocol is used with EEPROM selected (TM1=0). For SM bus access, SM bus protocol is used with SM bus selected (TM1=1).
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5.2
NON-TRANSPARENT MODE
In non-transparent bridge mode, base class code of PI7C9X130 is set to be 06h (bridge device). The subclass code is set to be 80h (other bridge). Programming interface is 00h. Hence, PI7C9X130 is not a subtractive decoding bridge. PI7C9X130 has type-0 configuration header if TM0 is set to 1 (non-transparent mode). The configuration registers are similar to a traditional PCI device. However, there is one set of configuration registers for the primary interface and another set of configuration registers for the secondary interface. In addition, CSRs (Control and Status Registers) are implemented to support the memory or IO transfers between the primary and secondary buses. The CSRs are accessed through memory transaction access within the lowest memory range of 4K Space (bit [64:12] are zeros). The non-transparent configuration registers can be accessed through several different ways (PCI Express, PCI, I2C, and SM bus). For PCI Express and PCI access, the type-0 configuration transactions need to be used. For I2C access, I2C bus protocol needs to be used through I2C bus interface. For SM bus access, SM bus protocol needs to be used through SM bus interface. The hardware pins (B5 and A5) are shared for I2C and SM bus interface. If TM1=0, pins B5 and A5 will be SCL and SDA for I2C interface respectively. If TM1=1, pins B5 and A5 will be SMBCLK and SMBDAT for SM Bus interface respectively. In non-transparent bridge mode, PI7C9X130 supports four or three memory BARs (Base Address Registers) and one or two IO BARs (Base Address Registers) depending on selection on the primary bus. Also, PI7C9X130 supports four or three memory BARs (Base Address Registers) and one or two IO BARs (Base Address Registers) depending on selection on the secondary bus. Offset 10h is defined to be primary CSR and downstream memory 0 BAR. Offset 14h is defined to be primary CSR and downstream IO BAR. Offset 18h is defined to be downstream memory 1 or IO BAR (selectable by CSR setup register). Offset 1Ch is defined to be downstream memory 2 BAR. Offset 20h and 24h are defined to be downstream memory 3 lower BAR and memory 3 upper BAR respectively to support 64-bit decoding. The direct offset translation of address from primary to secondary bus will be done by substituting the original Base Address at primary with the downstream Translation Base Address Register values and keeping the lower address bits the same to form a new address for forward the transaction to secondary bus. For downstream memory 2, it uses direct address translation. There is no lookup table for downstream memory address translation. Offset 50h is defined to be secondary CSR and upstream memory 0 BAR. Offset 54h is defined to be secondary CSR and upstream IO BAR. Offset 58h is defined to be upstream memory 1 or IO BAR (selectable by CSR setup register offset E4h). Offset 1Ch is defined to be upstream memory 2 BAR. Offset 60h and 64h are defined to be upstream memory 3 lower BAR and memory 3 upper BAR respectively to support 64-bit decoding. The direct offset translation of address from secondary to primary bus will be done by substituting the original Base Address at secondary with the upstream Translation Base Address Register values and keeping the lower address bits the same to form a new address for forward the transaction to primary bus. For upstream memory 2, it uses lookup table address translation method which using the original base address as index to select a new address on the upstream memory 2 lookup table based on the page and window size defined.
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Figure 5-1 Non-Transparent Registers
Non-transparent Registers
Primary CSR and Memory 0 BAR Downstream Memory 0 Translated Base Downstream Memory 0 Setup Primary CSR I/O BAR Downstream I/O or Memory 1 BAR Downstream I/O or Memroy 1 Translated Base Donwstream I/O or Memroy 1 Setup Downstream Memory 2 BAR Downstream Memory 2 Translated Base Downstream Memory 2 Setup Downstream Memory 3 BAR Downstream Memory 2 Setup Downstream Memory 3 BAR Downstream Memory 2 Setup Downstream Memory 3 BAR Secondary CSR Memory 0 BAR Upstream Memory 0 Translated Base Upstream Memory 0 Setup Secondary CSR I/O BAR Upstream I/O or Memory 1 BAR Upstream I/O or Memory 1 Translated Base Upstream I/O or Memory 1 Setup Upstream Memory 2 BAR Upstream Memory 2 Lookup Table Offset Upstream Memory 2 Lookup Table Data Upstream Memory 2 Lookup Table (64 32-bit entries) Upstream Memory 3 BAR Upstream Memory 3 Upper 32-bit BAR Upstream Memory 3 Setup Upstream Memory 3 Upper 32-bit Setup
Typical Access
Configuration access offset 10h Configuration access offset 98h Configuration access offset 9Ch Configuration access offset 14h Configuration access offset 18h Configuration access offset A8h Configuration access offset ACh Configuration access offset 1Fh Lower 4K I/O or Memory access offset 008h Lower 4K I/O or Memory access offset 00Ch Configuration access offset 23h Lower 4K I/O or Memory access offset 00Ch Configuration access offset 23h Lower 4K I/O or Memory access offset 00Ch Configuration access offset 23h Configuration access offset 50h Configuration access offset E0h Configuration access offset E4h Configuration access offset 54h Configuration access offset 58h Configuration access offset E8h Configuration access offset ECh Configuration access offset 5Fh Lower 4K I/O or Memory access offset 050h Lower 4K I/O or Memory access offset 054h Lower 4K I/O or Memory access offset 100h to 1FFh Configuration access offset 63h Configuration access offset 67h Lower 4K I/O or Memory access offset 34h Lower 4K I/O or Memory access offset 38h
6
6.1
PCI EXPRESS FUNCTIONAL OVERVIEW
TLP STRUCTURE
PCI Express TLP (Transaction Layer Packet) Structure is comprised of format, type, traffic class, attributes, TLP digest, TLP poison, and length of data payload. There are four TLP formats defined in PI7C9X130 based on the states of FMT [1] and FMT [0] as shown on Table 6-1. Figure 6-1 TLP Format
FMT [1]
0 0 1 1
FMT [0]
0 1 0 1
TLP FORMAT
3 double word, without data 4 double word, without data 3 double word, with data 4 double word, with data
Data payload of PI7C9X130 can range from 4 (1DW) to 256 (64DW) bytes. PI7C9X130 supports three TLP routing mechanisms. They are comprised of Address, ID, and Implicit routings. Address routing is being used for Memory and IO requests. ID based (bus, device, function numbers) routing is being used
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for configuration requests. Implicit routing is being used for message routing. There are two message groups (baseline and advanced switching). The baseline message group contains INTx interrupt signaling, power management, error signaling, locked transaction support, slot power limit support, vendor defined messages, hot-plug signaling. The other is advanced switching support message group. The advanced switching support message contains data packet and signal packet messages. Advanced switching is beyond the scope of PI7C9X130 implementation. The r [2:0] values of the "type" field will determine the destination of the message to be routed. All baseline messages must use the default traffic class zero (TC0).
6.2
VIRTUAL ISOCHRONOUS OPERATION
This section provides a summary of Virtual Isochronous Operation supported by PI7C9X130. Virtual Isochronous support is disabled by default. Virtual Isochronous feature can be turned on with setting bit [26] of offset 40h to one. Control bits are designated for selecting which traffic class (TC1-7) to be used for upstream (PCI Express-to-PCI). PI7C9X130 accepts only TC0 packets of configuration, IO, and message packets for downstream (PCI Express-to-PCI). If configuration, IO and message packets have traffic class other than TC0, PI7C9X130 will treat them as malformed packets. PI7C9X130 maps all downstream memory packets from PCI Express to PCI transactions regardless the virtual isochronous operation is enabled or not.
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7
CONFIGURATION REGISTERS
PI7C9X130 supports Type-0 (non-transparent bridge mode) and Type-1 (transparent bridge mode) configuration space headers and Capability ID of 01h (PCI power management) to 10h (PCI Express capability structure). With pin REVRSB = 0, device-port type (bit [7:4]) of capability register will be set to 7h (PCI Expressto-PCI/PIC-X bridge). When pin REVRSB = 1, device-port type (bit [7:4]) of capability register will be set to 8h (PCI/PCI-X-to-PCI Express bridge). PI7C9X130 supports PCI Express capabilities register structure with capability version set to 1h (bit [3:0] of offset 02h). When pin TM0=0, PI7C9X130 will be in transparent bridge mode and the configuration registers for transparent bridge should be used. When pin TM0=1, PI7C9X130 will be in non-transparent bridge mode and the configuration registers for non-transparent bridge should be used.
7.1
CONFIGURATION REGISTER MAP
PI7C9X130 supports capability pointer with PCI-X (ID=07h), PCI power management (ID=01h), PCI bridge sub-system vendor ID (ID=0Dh), PCI Express (ID=10h), vital product data (ID=03h), and message signaled interrupt (ID=05h). Hot swap (ID=06h) can be enabled by setting HSEN=1. Slot identification (ID=04h) is off by default and can be turned on through configuration programming. Figure 7-1 Configuration Register Map (00h - FFh)
Primary Bus Configuration Access for both Transparent and Non-transparent mode or Secondary Bus Configuration Access for Transparent Mode
01h - 00h 03h - 02h 05h - 04h
Secondary Bus Configuration Access for NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
01h - 00h 03h - 02h 45h - 44h
Vendor ID Device ID Command Register Primary Status Register Class Code and Revision ID Cacheline Size Register Primary Latency Timer
07h - 06h 0Bh - 08h 0Ch
47h - 46h 0Bh - 08h 4Ch
0Dh
4Dh
Vendor ID Device ID Primary Command Register Primary Status Register Class Code and Revision ID Primary Cacheline Size Register Primary Latency Timer
Yes1 Yes1 No
Yes5 Yes5 Yes
No Yes1 -
Yes Yes5 -
No
Yes
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Primary Bus Configuration Access for both Transparent and Non-transparent mode or Secondary Bus Configuration Access for Transparent Mode
0Eh 0Fh 13h - 10h
Secondary Bus Configuration Access for NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
4Eh 4Fh 53h - 50h
Header Type Register Reserved Reserved
17h - 14h 18h
57h - 54h 58h
Reserved Primary Bus Number Register Secondary Bus Number Register Subordinate Bus Number Register Secondary Latency Timer I/O Base Register I/O Limit Register Secondary Status Register Memory Base Register Memory Limit Register Prefetchable Memory Base Register Prefetchable Memory Limit Register Prefetchable Memory Base Upper 32-bit Register Prefetchable Memory Limit Upper 32-bit Register Prefetchable Memory Limit Upper 32-bit Register I/O Base Upper 16-bit Register I/O Limit Upper 16-bit Register
19h
59h
1Ah
5Ah
1Bh
5Bh
1Ch 1Dh 1Fh - 1Eh 21h - 20h 23h - 22h 25h - 24h
5Ch 5Dh 5Fh - 5Eh 61h - 60h 63h - 62h 65h - 64h
27h - 26h
67h - 66h
2Bh - 28h
2Bh - 28h
Header Type Register Reserved Primary CSR and Memory 0 BAR Primary CSR I/O BAR Downstream I/O or Memory 1 BAR Downstream I/O or Memory 1 BAR Downstream I/O or Memory 1 BAR Downstream I/O or Memory 1 BAR Downstream Memory 2 BAR Downstream Memory 2 BAR Downstream Memory 2 BAR Downstream Memory 3 BAR Downstream Memory 3 BAR Downstream Memory 3 Upper 32-bit BAR Downstream Memory 3 Upper 32-bit BAR Reserved
No No
Yes Yes
No No
Yes Yes
No
Yes
No
Yes
No
Yes
No No No No No No
Yes Yes Yes Yes Yes Yes
No
Yes
No
Yes
2Dh - 2Ch
2Dh - 2Ch
Subsystem Vendor ID
Yes
2
Yes
5
2Fh - 2Eh
2Fh - 2Eh
Subsystem ID
Yes
2
Yes
5
31h - 30h 33h - 32h
31h - 30h 33h - 32h
Reserved Reserved
No No
Yes Yes
Page 30 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Primary Bus Configuration Access for both Transparent and Non-transparent mode or Secondary Bus Configuration Access for Transparent Mode
34h 37h - 35h 3Bh - 38h 3Ch 3Dh 3Eh 3Fh 41h - 40h
Secondary Bus Configuration Access for NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
34h 37h - 35h 3Bh - 38h 7Ch 7Dh 7Eh 7Fh 41h - 40h
Capability Pointer Reserved Reserved Interrupt Line Interrupt Pin Bridge Control Bridge Control PCI Data Buffering Control Chip Control 0 Reserved
43h - 42h 45h - 44h
43h - 42h 05h - 04h
47h - 46h 4Bh - 48h 4Ch
07h - 06h 4Bh - 48h 0Ch
Reserved Arbiter Mode, Enable, Priority Reserved
4Dh 4Eh 4Fh 53h - 50h
0Dh 0Eh 0Fh 13h - 10h
Reserved Reserved Reserved Reserved
57h - 54h 5Bh - 58h 5Fh - 5Ch 63h - 60h 67h - 64h
17h - 14h 1Bh - 18h 1Fh - 1Ch 23h - 20h 27h - 24h
Reserved Reserved Reserved Reserved Reserved
69h - 68h 6Ah
69h - 68h 6Ah
PCI Express Tx and Rx Control Reserved
6Bh 6Dh - 6Ch
6Bh 6Dh - 6Ch
Reserved Reserved
Capability Pointer Reserved Reserved Primary Interrupt Line Primary Interrupt Pin Primary Min_Gnt Primary Max_Lat PCI Data Buffering Control Chip Control 0 Secondary Command Register Secondary Status Register Arbiter Mode, Enable, Priority Secondary Cacheline Size Register Secondary Status Register Header Type Reserved Secondary CSR and Memory 0 BAR Secondary CSR I/O BAR Upstream I/O or Memory 1 BAR Upstream Memory 2 BAR Upstream Memory 3 BAR Upstream Memory 3 Upper 32-bit BAR PCI Express Tx and Rx Control Memory Address Forwarding Control Reserved Subsystem d
No No No No No Yes Yes
3 3
Yes Yes Yes Yes Yes Yes Yes
3 3
Yes
Yes
Yes No
Yes Yes
No Yes No
Yes Yes Yes
No No No
Yes Yes Yes
No No No No No
Yes Yes Yes Yes Yes
Yes Yes
3
Yes Yes
3
No 2 Yes
Yes 5 Yes
Page 31 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Primary Bus Configuration Access for both Transparent and Non-transparent mode or Secondary Bus Configuration Access for Transparent Mode
6Fh - 6Eh 73h - 70h
Secondary Bus Configuration Access for NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
6Fh - 6Eh 73h - 70h
Reserved EEPROM (I2C) Control and Status Register Hot Swap Capability GPIO Data and Control (20 bits) Reserved (12 bits)
Vendor ID Subsystem ID EEPROM (I2C) Control and status Register Hot Swap Capability GPIO Data and Control (20 bits) Bridge Control and Status (10 bits) Reserved (2 bits) Secondary Interrupt Line Secondary Interrupt Pin Secondary Min_Gnt Secondary Max_Lat PCI-X Capability PCI-X Bridge Status Upstream Split Transaction Downstream Split Transaction Power Management Capability Power Management Control and Status Downstream Memory 0 Translated Base Downstream Memory 0 Setup Slot ID Capability PCI Clock and CLKRUN Control Downstream I/O or Memory 1 Translated
Yes No
2
Yes Yes
5
77h - 74h 7Bh - 78h
77h - 74h 7Bh - 78h
No No
Yes Yes
No
No
No No No Yes Yes
3 3
No Yes Yes Yes Yes
3 3
7Ch 7Dh 7Eh 7Fh 83h - 80h 87h - 84h 8Bh - 88h 8Fh - 8Ch
3Ch 3Dh 3Eh 3Fh 83h - 80h 87h - 84h 8Bh - 88h 8Fh - 8Ch
Reserved Reserved Reserved Reserved PCI-X Capability PCI-X Bridge Status Upstream Split Transaction Downstream Split Transaction Power Management Capability Power Management Control and Status Reserved
No No No No
Yes Yes Yes Yes
93h - 90h
93h - 90h
Yes
Yes
97h - 94h
97h - 94h
No
Yes
9Bh - 98h
9Bh - 98h
No
3
Yes
3
9Fh - 9Ch
9Fh - 9Ch
Reserved
Yes
Yes
A3h - A0h A7h - A4h
A3h - A0h A7h - A4h
ABh - A8h
ABh - A8h
Slot ID Capability PCI Clock and CLKRUN Control SSID and SSVID Capability
No Yes
Yes Yes
No
Yes
Page 32 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Primary Bus Configuration Access for both Transparent and Non-transparent mode or Secondary Bus Configuration Access for Transparent Mode
Afh - ACh
Secondary Bus Configuration Access for NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
Afh - ACh
B3h - B0h B7h - B4h BBh - B8h BFh - BCh C3h - C0h C7h - C4h CBh - C8h CFh - CCh
B3h - B0h B7h - B4h BBh - B8h BFh - BCh C3h - C0h C7h - C4h CBh - C8h CFh - CCh
D3h - D0h
D3h - D0h
D6h - D4h
D6h - D4h
D7h
D7h
DBh - D8h DFh - DCh E3h - E0h
DBh - D8h DFh - DCh E3h - E0h
Subsystem ID and Subsystem Vendor ID PCI Express Capability Device Capability Device Control and Status Link Capability Link Control and Status Slot Capability Slot Control and Status XPIP Configuration Register 0 XPIP Configuration Register 1 XPIP Configuration Register 2 Hot Swap Switch debounce counter VPD Capability Register VPD Data Register Reserved
E7h - E4h EBh - E8h
E7h - E4h EBh - E8h
Reserved Reserved
EFh - ECh
EFh - ECh
Reserved
F3h - F0h F7h - F4h FBh - F8h FFh - FCh
F3h - F0h F7h - F4h FBh - F8h FFh - FCh
MSI Capability Register Message Address Message Upper Address Message Data
Base Downstream I/O or Memory 1 Setup PCI Express Capability Device Capability Device Control and Status Link Capability Link Control and Status Slot Capability Slot Control and Status XPIP Configuration Register 0 XPIP Configuration Register 1 XPIP Configuration Register 2 Hot Swap Switch debounce counter VPD Capability Register VPD Data Register Upstream Memory 0 Translated Base Upstream Memory 0 setup Upstream I/O or Memory 1 Translated Base Upstream I/O or Memory 1 Setup MSI Capability Register Message Address Message Upper Address Message Data
Yes
Yes
No Yes No Yes No No No Yes
Yes Yes Yes Yes Yes Yes Yes Yes
Yes
Yes
Yes
Yes
Yes
Yes
No Yes4 No
3
Yes Yes Yes
3
Yes
Yes
No
3
Yes
3
Yes
Yes
No No No No
Yes Yes Yes Yes
Note 1: When masquerade is enabled, it is pre-loadable. Note 2: When both masquerade and non-transparent mode are enabled, it is pre-loadable.
Page 33 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Note 3: When non-transparent mode is enabled, it is pre-loadable. Note 4: The VPD data is read/write through I2C during VPD operation. Note 5: Read access only.
7.2
PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP
PI7C9X130 also supports PCI Express Extended Capabilities with from 257-byte to 4096-byte space. The offset range is from 100h to FFFh. The offset 100h is defined for Advance Error Reporting (ID=0001h). The offset 150h is defined for Virtual Channel (ID=0002h). Figure 7-2 PCI Express Extended Capability Register Map (100h - FFFh)
Primary Bus Configuration Access for both Transparent and Non-transparent mode or Secondary Bus Configuration Access for Transparent Mode
103h - 100h
Secondary Bus Configuration Access for NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
103h - 100h
107h - 104h 10Bh - 108h 10Fh - 10Ch 113h - 110h 117h - 114h 11Bh - 118h 12Bh - 11Ch 12Fh - 12Ch
107h - 104h 10Bh - 108h 10Fh - 10Ch 113h - 110h 117h - 114h 11Bh - 118h 12Bh - 11Ch 12Fh - 12Ch
133h - 130h
133h - 130h
137h - 134h
137h - 134h
13Bh - 138h 14Bh - 13Ch
13Bh - 138h 14Bh - 13Ch
14Fh - 14Ch 153h - 150h 157h - 154h 15Bh - 158h
14Fh - 14Ch 153h - 150h 157h - 154h 15Bh - 158h
Advanced Error Reporting (AER) Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Severity Correctable Error Status Correctable Error Mask AER Control Header Log Register Secondary Uncorrectable Error Status Secondary Uncorrectable Error Mask Secondary Uncorrectable Severity Secondary AER Control Secondary Header Log Register Reserved VC Capability Port VC Capability 1 Port VC Capability 2
Advanced Error Reporting (AER) Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Severity Correctable Error Status Correctable Error Mask AER Control Header Log Register Secondary Uncorrectable Error Status Secondary Uncorrectable Error Mask Secondary Uncorrectable Severity Secondary AER Control Secondary Header Log Register Reserved VC Capability Port VC Capability 1 Port VC Capability 2
No
Yes
5
No No No No No No No No
Yes Yes Yes Yes Yes Yes Yes Yes
No
Yes
No
Yes
No No
Yes Yes
No No No No
Yes Yes Yes Yes
Page 34 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Primary Bus Configuration Access for both Transparent and Non-transparent mode or Secondary Bus Configuration Access for Transparent Mode
15Fh - 15Ch 163h - 160h 167h - 164h 16Bh - 168h 2FFh - 170h 303h - 300h
Secondary Bus Configuration Access for NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
SM Bus Access
15Fh - 15Ch 163h - 160h 167h - 164h 16Bh - 168h 2FFh - 170h 503h - 500h
307h - 304h
507h - 504h
30Fh - 308h 310h
50Fh - 508h 510h
4FFh - 314h 503h - 500h 504h 50Fh - 505h 510h FFFh - 514h
4FFh - 314h 303h - 300h 304h 30Fh - 305h 310h FFFh - 514h
Port VC Status and Control VC0 Resource Capability VC0 Resource Control VC0 Resource Status Reserved Extended GPIO Data and Control Extended GPI/GPO Data and Control Reserved Replay and Acknowledge Latency Timer Reserved Reserved Reserved Reserved Reserved Reserved
Port VC Status and Control VC0 Resource Capability VC0 Resource Control VC0 Resource Status Reserved Extended GPIO Data and Control Extended GPI/GPO Data and Control Reserved Replay and Acknowledge Latency Timer Reserved Reserved Reserved Reserved Reserved Reserved
No No No No No No
Yes Yes Yes Yes Yes Yes
No
Yes
No Yes
No Yes
No No No No No No
No No No No No No
Note 5: Read access only.
7.3
CONTROL AND STATUS REGISTER MAP
Figure 7-3 Control and Status Register (CSR) Map (000h - FFFh)
PCI Express / PCI Memory Offset
007h - 000h 00Bh - 008h
SM Bus Offset
207h - 200h 20Bh - 208h
Register Name
Reserved Downstream Memory 2 Translated Base Downstream Memory 2 Setup Downstream Memory 3 Translated Base Downstream Memory 3 Setup
Reset Value
EEPROM (I2C) Access
No No
SM Bus Access
Yes Yes
0 XXXX_XXXXh
00Fh - 00Ch
20Fh - 20Ch
0000_0000h
Yes
Yes
013h - 010h
213h - 210h
XXXX_XXXXh
No
Yes
017h - 014h
217h - 214h
0000_0000h
Yes
Yes
Page 35 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
PCI Express / PCI Memory Offset
01Bh - 018h
SM Bus Offset
21Bh - 218h
Register Name
Downstream Memory 3 Upper 32-bit Setup Reserved Reserved Upstream Memory 3 Setup Upstream Memory 3 Upper 32-bit Setup Reserved Lookup Table Offset Register Reserved Lookup Table Data Register Upstream Page Boundary IRQ 0 Upstream Page Boundary IRQ 1 Upstream Page Boundary IRQ Mask 0 Upstream Page Boundary IRQ Mask 1 Reserved Primary Clear IRQ Register Secondary Clear IRQ Register Primary Set IRQ Register Secondary Set IRQ Register Primary Clear IRQ Mask Register Secondary Clear IRQ Mask Register Primary Set IRQ Mask Register Secondary Set IRQ Mask Register Reserved Scratch pad 0 Scratch pad 1 Scratch pad 2 Scratch pad 3 Scratch pad 4 Scratch pad 5 Scratch pad 6 Scratch pad 7 Reserved
Reset Value
EEPROM (I2C) Access
Yes
SM Bus Access
Yes
0000_0000h
02Fh - 01Ch 033h - 030h 037h - 034h
22Fh - 21Ch 233h - 230h 237h - 234h
0 X 0000_0000h
No No Yes
Yes Yes Yes
03Bh - 038h
21Bh - 218h
0000_0000h
Yes
Yes
04Fh - 03Ch 050h 053h - 051h 057h - 054h 05Bh - 058h
24Fh - 23Ch 250h 253h - 251h 257h - 254h 25Bh - 258h
0 XXh 0 XXXX_XXXXh 0000_0000h
No No No No No
Yes Yes Yes Yes Yes
05Fh - 05Ch
25Fh - 25Ch
0000_0000h
No
Yes
063h - 060h
263h - 260h
FFFF_FFFFh
No
Yes
067h - 064h
267h - 264h
FFFF_FFFFh
No
Yes
06Fh - 068h 071h - 070h 073h - 072h 075h - 074h 077h - 076h 079h - 078h
26Fh - 268h 271h - 270h 273h - 272h 275h - 274h 277h - 276h 279h - 278h
0 0000h 0000h 0000h 0000h FFFFh
No No No No No No
Yes Yes Yes Yes Yes Yes
07Bh - 07Ah
27Bh - 27Ah
FFFFh
No
Yes
07Dh - 07Ch
27Dh - 27Ch
FFFFh
No
Yes
07Fh - 07Eh
27Fh - 27Eh
FFFFh
No
Yes
09Fh - 080h 0A3h - 0A0h 0A7h - 0A4h 0ABh - 0A8h 0AFh - 0ACh 0B3h - 0B0h 0B7h - 0B4h 0BBh - 0B8h 0BFh - 0BCh 0FFh - 0C0h
29Fh - 280h 2A3h - 2A0h 2A7h - 2A4h 2ABh - 2A8h 2AFh - 2ACh 2B3h - 2B0h 2B7h - 2B4h 2BBh - 2B8h 2BCh - 2BFh 2FFh - 2C0h
0 XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh 0
No No No No No No No No No No
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Page 36 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
PCI Express / PCI Memory Offset
1FFh - 100h
SM Bus Offset
3FFh - 300h
Register Name
Upstream Memory 2 Lookup Table Reserved
Reset Value
EEPROM (I2C) Access
No
SM Bus Access
Yes
0
FFFh - 200h
11FFh - 400h
0
No
Yes
7.4
PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE
The following section describes the configuration space when the device is in transparent mode. The descriptions for different register type are listed as follow:
Register Type
RO ROS RW RWC RWS RWCS
Descriptions
Read Only Read Only and Sticky Read/Write Read/Write "1" to clear Read/Write and Sticky Read/Write "1" to clear and Sticky
7.4.1
VENDOR ID - OFFSET 00h
Bit
15:0
Function
Vendor ID
Type
RO
Description
Identifies Pericom as the vendor of this device. Returns 12D8h when read.
7.4.2
DEVICE ID - OFFSET 00h
Bit
31:16
Function
Device ID
Type
RO
Description
Identifies this device as the PI7C9X130. Returns E130 when read.
7.4.3
COMMAND REGISTER - OFFSET 04h
Bit
0
Function
I/O Space Enable
Type
RW
Description
0: Ignore I/O transactions on the primary interface 1: Enable response to memory transactions on the primary interface Reset to 0 0: Ignore memory read transactions on the primary interface 1: Enable memory read transactions on the primary interface Reset to 0 0: Do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on the secondary interface 1: Enable the bridge to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface. If the primary of the reverse bridge is PCI-X mode, the bridge is allowed to initiate a split completion transaction regardless of the status bit. Reset to 0
1
Memory Space Enable
RW
2
Bus Master Enable
RW
Page 37 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
3
Function
Special Cycle Enable
Type
RO
Description
0: PI7C9X130 does not respond as a target to Special Cycle transactions, so this bit is defined as Read-Only and must return 0 when read Reset to 0 0: PI7C9X130 does not originate a Memory Write and Invalidate transaction. Implements this bit as Read-Only and returns 0 when read (unless forwarding a transaction for another master). This bit will be ignored in PCI-X mode. Reset to 0 This bit applies to reverse bridge only. 0: Ignore VGA palette access on the primary 1: Enable positive decoding response to VGA palette writes on the primary interface with I/O address bits AD [9:0] equal to 3C6h, 3C8h, and 3C9h (inclusive of ISA alias; AD [15:0] are not decoded and may be any value) Reset to 0 0: May ignore any parity error that is detected and take its normal action 1: This bit if set, enables the setting of Master Data Parity Error bit in the Status Register when poisoned TLP received or parity error is detected and takes its normal action Reset to 0 Wait cycle control not supported Reset to 0 0: Disable 1: Enable PI7C9X130 in forward bridge mode to report non-fatal or fatal error message to the Root Complex. Also, in reverse bridge mode to assert SERR_L on the primary interface Reset to 0 Fast back-to-back enable not supported Reset to 0 This bit applies to reverse bridge only. 0: INTA_L, INTB_L, INTC_L, and INTD_L can be asserted on PCI interface 1: Prevent INTA_L, INTB_L, INTC_L, and INTD_L from being asserted on PCI interface Reset to 0 Reset to 00000
4
Memory Write and Invalidate Enable
RO
5
VGA Palette Snoop Enable
RO / RW
6
Parity Error Response Enable
RW
7
Wait Cycle Control
RO
8
SERR_L Enable Bit
RW
9
Fast Back-to-Back Enable Interrupt Disable
RO
10
RO / RW
15:11
Reserved
RO
7.4.4
PRIMARY STATUS REGISTER - OFFSET 04h
Bit
19:16 20
Function
Reserved Capability List Capable
Type
RO RO
Description
Reset to 0000 1: PI7C9X130 supports the capability list (offset 34h in the pointer to the data structure) Reset to 1 This bit applies to reverse bridge only. 1: 66MHz capable Reset to 0 when forward bridge or 1 when reverse bridge. Reset to 0
21
66MHz Capable
RO
22
Reserved
RO
Page 38 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
23
Function
Fast Back-to-Back Capable
Type
RO
Description
This bit applies to reverse bridge only. 1: Enable fast back-to-back transactions Reset to 0 when forward bridge or 1 when reverse bridge in PCI mode. Bit set if its Parity Error Enable bit is set and either of the conditions occurs on the primary: FORWARD BRIDGE - * Receives a completion marked poisoned * Poisons a write request REVERSE BRIDGE - * Detected parity error when receiving data or Split Response for read * Observes P_PERR_L asserted when sending data or receiving Split Response for write * Receives a Split Completion Message indicating data parity error occurred for non-posted write Reset to 0 These bits apply to reverse bridge only. 00: 01: 10: 11: fast DEVSEL_L decoding medium DEVSEL_L decoding slow DEVSEL_L decoding reserved
24
Master Data Parity Error Detected
RWC
26:25
DEVSEL_L Timing (medium decode)
RO
27
Signaled Target Abort
RWC
Reset to 00 when forward bridge or 01 when reverse bridge. FORWARD BRIDGE - This bit is set when PI7C9X130 completes a request using completer abort status on the primary REVERSE BRIDGE - This bit is set to indicate a target abort on the primary Reset to 0 FORWARD BRIDGE - This bit is set when PI7C9X130 receives a completion with completer abort completion status on the primary REVERSE BRIDGE - This bit is set when PI7C9X130 detects a target abort on the primary Reset to 0 FORWARD BRIDGE - This bit is set when PI7C9X130 receives a completion with unsupported request completion status on the primary REVERSE BRIDGE - This bit is set when PI7C9X130 detects a master abort on the primary FORWARD BRIDGE - This bit is set when PI7C9X130 sends an ERR_FATAL or ERR_NON_FATAL message on the primary REVERSE BRIDGE - This bit is set when PI7C9X130 asserts SERR_L on the primary Reset to 0 FORWARD BRIDGE - This bit is set when poisoned TLP is detected on the primary REVERSE BRIDGE - This bit is set when address or data parity error is detected on the primary Reset to 0
28
Received Target Abort
RWC
29
Received Master Abort
RWC
30
Signaled System Error
RWC
31
Detected Parity Error
RWC
Page 39 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.5
REVISION ID REGISTER - OFFSET 08h
Bit
7:0
Function
Revision
Type
RO
Description
Reset to 00000000
7.4.6
CLASS CODE REGISTER - OFFSET 08h
Bit
15:8
Function
Programming Interface Sub-Class Code
Type
RO
Description
Subtractive decoding of PCI-PCI bridge not supported Reset to 00000000 Sub-Class Code 00000100: PCI-to-PCI bridge Reset to 00000100 Base class code 00000110: Bridge Device Reset to 00000110
23:16
RO
31:24
Base Class Code
RO
7.4.7
CACHE LINE SIZE REGISTER - OFFSET 0Ch
Bit
1:0
Function
Reserved
Type
RO
Description
Bit [1:0] not supported Reset to 00 1: Cache line size = 4 double words Reset to 0 1: Cache line size = 8 double words Reset to 0 1: Cache line size = 16 double words Reset to 0 1: Cache line size = 32 double words Reset to 0 Bit [7:6] not supported Reset to 00
2
Cache Line Size
RW
3
Cache Line Size
RW
4
Cache Line Size
RW
5
Cache Line Size
RW
7:6
Reserved
RO
7.4.8
PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch
Bit
15:8
Function
Primary Latency Timer
Type
RO / RW
Description
8 bits of primary latency timer in PCI/PCI-X FORWARD BRIDGE - RO with reset to 00h REVERSE BRIDGE - RW with reset to 00h in PCI mode or 40h in PCI-X mode
Page 40 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.4.9
HEADER TYPE REGISTER - OFFSET 0Ch
Bit
22:16
Function
PCI-to-PCI bridge configuration Single Function Device Reserved
Type
RO
Description
PCI-to-PCI bridge configuration (10 - 3Fh) Reset to 0000001 0: Indicates single function device Reset to 0 Reset to 00h
23
RO
31:24
RO
7.4.10 7.4.11
RESERVED REGISTERS - OFFSET 10h TO 17h PRIMARY BUS NUMBER REGISTER - OFFSET 18h
Bit
7:0
Function
Primary Bus Number
Type
RW
Description
Reset to 00h
7.4.12
SECONDARY BUS NUMBER REGISTER - OFFSET 18h
Bit
15:8
Function
Secondary Bus Number
Type
RW
Description
Reset to 00h
7.4.13
SUBORDINATE BUS NUMBER REGISTER - OFFSET 18h
Bit
23:16
Function
Subordinate Bus Number
Type
RW
Description
Reset to 00h
7.4.14
SECONDARY LATENCY TIMER REGISTER - OFFSET 18h
Bit
31:24
Function
Secondary Latency Timer
Type
RW / RO
Description
Secondary latency timer in PCI / PCI-X mode FORWARD BRIDGE - RW with reset to 00h in PCI mode or 40h in PCI-X mode REVERSE BRIDGE - RO with reset to 00h
7.4.15
I/O BASE REGISTER - OFFSET 1Ch
Bit
1:0
Function
32-bit I/O Addressing Support Reserved
Type
RO
Description
01: Indicates PI7C9X130 supports 32-bit I/O addressing Reset to 01 Reset to 00
3:2
RO
Page 41 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
7:4
Function
I/O Base
Type
RW
Description
Indicates the I/O Base (0000_0000h) Reset to 0000
7.4.16
I/O LIMIT REGISTER - OFFSET 1Ch
Bit
9:8
Function
32-bit I/O Addressing Support Reserved I/O Base
Type
RO
Description
01: Indicates PI7C9X130 supports 32-bit I/O addressing Reset to 01 Reset to 00 Indicates the I/O Limit (0000_0FFFh) Reset to 0000
11:10 15:12
RO RW
7.4.17
SECONDARY STATUS REGISTER - OFFSET 1Ch
Bit
20:16 21
Function
Reserved 66MHz Capable
Type
RO RO
Description
Reset to 00000 Indicates PI7C9X130 is 66MHz capable Reset to 1 Reset to 0 FORWARD BRIDGE: reset to 1 when secondary bus is in PCI mode (supports fast back-to-back transactions) or reset to 0 when secondary bus is in PCI-X mode (does not support fast back-to-back transactions) REVERSE BRIDGE: reset to 0 (does not support fast back-to-back transactions) This bit is set if its parity error enable bit is set and either of the conditions occur on the primary: FORWARD BRIDGE - * Detected parity error when receiving data or split response for read * Observes S_PERR_L asserted when sending data or receiving split response for write * Receives a split completion message indicating data parity error occurred for non-posted write REVERSE BRIDGE - * Receives a completion marked poisoned * Poisons a write request Reset to 0 These bits apply to forward bridge only. 01: medium DEVSEL_L decoding Reset to 01 when forward mode or 00 when reverse mode. FORWARD BRIDGE - Bit is set when PI7C9X130 signals target abort REVERSE BRIDGE - Bit is set when PI7C9X130 completes a request using completer abort completion status Reset to 0
22 23
Reserved Fast Back-to-Back Capable
RO RO
24
Master Data Parity Error Detected
RWC
26:25
DEVSEL_L Timing (medium decoding)
RO
27
Signaled Target Abort
RWC
Page 42 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
28
Function
Received Target Abort
Type
RWC
Description
FORWARD BRIDGE - Bit is set when PI7C9X130 detects target abort on the secondary interface REVERSE BRIDGE - Bit is set when PI7C9X130 receives a completion with completer abort completion status on the secondary interface Reset to 0 FORWARD BRIDGE - Bit is set when PI7C9X130 detects master abort on the secondary interface REVERSE BRIDGE - Bit is set when PI7C9X130 receives a completion with unsupported request completion status on the primary interface Reset to 0 FORWARD BRIDGE - Bit is set when PI7C9X130 detects SERR_L assertion on the secondary interface REVERSE BRIDGE - Bit is set when PI7C9X130 receives an ERR_FATAL or ERR_NON_FATAL message on the secondary interface Reset to 0 FORWARD BRIDGE - Bit is set when PI7C9X130 detects address or data parity error REVERSE BRIDGE - Bit is set when PI7C9X130 detects poisoned TLP on secondary interface Reset to 0
29
Received Master Abort
RWC
30
Received System Error
RWC
31
Detected Parity Error
RWC
7.4.18
MEMORY BASE REGISTER - OFFSET 20h
Bit
3:0 15:4
Function
Reserved Memory Base
Type
RO RW
Description
Reset to 0000 Memory Base (80000000h) Reset to 800h
7.4.19
MEMORY LIMIT REGISTER - OFFSET 20h
Bit
19:16 31:20
Function
Reserved Memory Limit
Type
RO RW
Description
Reset to 0000 Memory Limit (000FFFFFh) Reset to 000h
7.4.20
PREFETCHABLE MEMORY BASE REGISTER - OFFSET 24h
Bit
3:0
Function
64-bit Addressing Support Prefetchable Memory Base
Type
RO
Description
0001: Indicates PI7C9X130 supports 64-bit addressing Reset to 0001 Prefetchable Memory Base (00000000_80000000h) Reset to 800h
15:4
RW
Page 43 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.21
PREFETCHABLE MEMORY LIMIT REGISTER - OFFSET 24h
Bit
19:16
Function
64-bit Addressing Support Prefetchable Memory Limit
Type
RO
Description
0001: Indicates PI7C9X130 supports 64-bit addressing Reset to 0001 Prefetchable Memory Limit (00000000_000FFFFFh) Reset to 000h
31:20
RW
7.4.22
PREFETCHABLE BASE UPPER 32-BIT REGISTER - OFFSET 28h
Bit
31:0
Function
Prefetchable Base Upper 32-bit
Type
RW
Description
Bit [63:32] of prefetchable base Reset to 00000000h
7.4.23
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER - OFFSET 2Ch
Bit
31:0
Function
Prefetchable Limit Upper 32-bit
Type
RW
Description
Bit [63:32] of prefetchable limit Reset to 00000000h
7.4.24
I/O BASE UPPER 16-BIT REGISTER - OFFSET 30h
Bit
15:0
Function
I/O Base Upper 16bit
Type
RW
Description
Bit [31:16] of I/O Base Reset to 0000h
7.4.25
I/O BASE UPPER 16-BIT REGISTER - OFFSET 30h
Bit
31:16
Function
I/O Limit Upper 16bit
Type
RW
Description
Bit [31:16] of I/O Limit Reset to 0000h
7.4.26
CAPABILITY POINTER - OFFSET 34h
Bit
31:8 7:0
Function
Reserved Capability Pointer
Type
RO RO
Description
Reset to 0 Capability pointer to 80h Reset to 80h
Page 44 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.27
EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h
Bit
31:0
Function
Expansion ROM Base Address
Type
RO
Description
Expansion ROM not supported. Reset to 00000000h
7.4.28
INTERRUPT LINE REGISTER - OFFSET 3Ch
Bit
7:0
Function
Interrupt Line
Type
RW
Description
These bits apply to reverse bridge only. For initialization code to program to tell which input of the interrupt controller the PI7C9X130's INTA_L in connected to. Reset to 00000000
7.4.29
INTERRUPT PIN REGISTER - OFFSET 3Ch
Bit
15:8
Function
Interrupt Pin
Type
RO
Description
These bits apply to reverse bridge only. Designates interrupt pin INTA_L, is used Reset to 00h when forward mode or 01h when reverse mode.
7.4.30
BRIDGE CONTROL REGISTER - OFFSET 3Ch
Bit
16
Function
Parity Error Response Enable
Type
RW
Description
0: Ignore parity errors on the secondary 1: Enable parity error detection on secondary FORWARD BRIDGE - Controls the response to uncorrectable address attribute and data errors on the secondary REVERSE BRIDGE - Controls the setting of the master data parity error bit in response to a received poisoned TLP from the secondary (PCIe link) Reset to 0 0: Disable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL 1: Enable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL Reset to 0 (FORWARD BRIDGE) RO bit for REVERSE BRIDGE 0: Forward downstream all I/O addresses in the address range defined by the I/O Base and Limit registers 1: Forward upstream all I/O addresses in the address range defined by the I/O Base and Limit registers that are in the first 64KB of PCI I/O address space (top 768 bytes of each 1KB block) Reset to 0
17
SERR_L Enable
RW
18
ISA Enable
RW
Page 45 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
19
Function
VGA Enable
Type
RW
Description
0: Do not forward VGA compatible memory and I/O addresses from the primary to secondary, unless they are enabled for forwarding by the defined I/O and memory address ranges 1: Forward VGA compatible memory and I/O addresses from the primary and secondary (if the I/O enable and memory enable bits are set), independent of the ISA enable bit 0: Execute 10-bit address decodes on VGA I/O accesses 1: Execute 16-bit address decode on VGA I/O accesses Reset to 0 0: Do not report master aborts (return FFFFFFFFh on reads and discards data on write) 1: Report master abort by signaling target abort if possible or by the assertion of SERR_L (if enabled). Reset to 0 0: Do not force the assertion of RESET_L on secondary PCI bus for forward bridge, or do not generate a hot reset on the PCIe link for reverse bridge 1: Force the assertion of RESET_L on secondary PCI bus for forward bridge, or generate a hot reset on the PCIe link for reverse bridge Reset to 0 Fast back-to-back not supported Reset to 0 0: Primary discard timer counts 215 PCI clock cycles 1: Primary discard timer counts 210 PCI clock cycles FORWARD BRIDGE - Bit is RO and ignored by the PI7C9X130 Reset to 0 0: Secondary discard timer counts 215 PCI clock cycles 1: Secondary discard timer counts 210 PCI clock cycles REVERSE BRIDGE - Bit is RO and ignored by PI7C9X130 Reset to 0 Bit is set when the discard timer expires and a delayed completion is discarded at the PCI interface for the forward or reverse bridge Reset to 0 Bit is set to enable to generate ERR_NONFATAL or ERR_FATAL for forward bridge, or assert P_SERR_L for reverse bridge as a result of the expiration of the discard timer on the PCI interface. Reset to 0 Reset to 0000
20
VGA 16-bit Decode
RW
21
Master Abort Mode
RW
22
Secondary Interface Reset
RW
23
Fast Back-to-Back Enable Primary Master Timeout
RO
24
RW
25
Secondary Master Timeout
RW
26
Master Timeout Status
RWC
27
Discard Timer SERR_L Enable
RW
31:28
Reserved
RO
7.4.31
PCI DATA BUFFERING CONTROL REGISTER - OFFSET 40h
Bit
0
Function
Secondary Internal Arbiter's PARK Function Memory Read Prefetching Dynamic Control Disable
Type
RW
Description
0: Park to the last master 1: Park to PI7C9X130 secondary port Reset to 0 0: Enable memory read prefetching dynamic control for PCI to PCIe read 1: Disable memory read prefetching dynamic control for PCI to PCIe read Reset to 0
1
RW
Page 46 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
2
Function
Completion Data Prediction Control
Type
RW
Description
0: Enable completion data prediction for PCI to PCIe read. 1: Disable completion data prediction Reset to 0 Reset to 0 These two bits are ignored in PCI-X mode. 00: One cache line prefetch if memory read multiple address is in prefetchable range at the PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface, and the PI7C9X130 will keep remaining data after it disconnects the external master during burst read with read multiple command until the discard timer expires 10: Full prefetch if address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X130 will keep remaining data after the read multiple is terminated either by an external master or by the PI7C9X130, until the discard time expires Reset to 10 These two bits are ignored in PCI-X mode. 00: Once cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X130 will keep remaining data after it is disconnected by an external master during burst read with read line command, until discard timer expires 10: Full prefetch if memory read line address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X130 will keep remaining data after the read line is terminated either by an external master or by the PI7C9X130, until the discard timer expires Reset to 00 00: One cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Reserved 10: Full prefetch if memory read address is in prefetchable range at PCI interface 11: Disconnect on the first DWORD Reset to 00 0: Retry any master at PCI bus that repeats its transaction with command code changes. 1: Allows any master at PCI bus to change memory command code (MR, MRL, MRM) after it has received a retry. The PI7C9X130 will complete the memory read transaction and return data back to the master if the address and byte enables are the same. Reset to 0 Reset to 0 Maximum byte count is used by the PI7C9X130 when generating memory read requests on the PCIe link in response to a memory read initiated on the PCI bus and bit [9:8], bit [7:6], and bit [5:4] are set to "full prefetch". 000: 001: 010: 011: 100: 101: 110: 111: 512 bytes (default) 128 bytes 256 bytes 512 bytes 1024 bytes 2048 bytes 4096 bytes 512 bytes
3 5:4
Reserved PCI Read Multiple Prefetch Mode
RO RW
7:6
PCI Read Line Prefetch Mode
RW
9:8
PCI Read Prefetch Mode
RW
10
PCI Special Delayed Read Mode Enable
RW
11 14:12
Reserved Maximum Memory Read Byte Count
RO RW
Reset to 000
Page 47 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.32
CHIP CONTROL 0 REGISTER - OFFSET 40h
Bit
15
Function
Flow Control Update Control
Type
RW
Description
0: Flow control is updated for every two credits available 1: Flow control is updated for every on credit available Reset to 0 0: The PCI retry counter has not expired since the last reset 1: The PCI retry counter has expired since the last reset Reset to 0 00: No expiration limit 01: Allow 256 retries before expiration 10: Allow 64K retries before expiration 11: Allow 2G retries before expiration Reset to 00 0: Enable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge control register) 1: Disable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge control register) Reset to 0 0: Use bit [24] offset 3Ch for forward bridge or bit [25] offset 3Ch for reverse bridge to indicate how many PCI clocks should be allowed before the PCI discard timer expires 1: 64 PCI clocks allowed before the PCI discard timer expires Reset to 0 00: Timer expires at 25us 01: Timer expires at 0.5ms 10: Timer expires at 5ms 11: Timer expires at 25ms Reset to 01 0: Enable out-of-order capability between delayed transactions 1: Disable out-of-order capability between delayed transactions Reset to 0 00: Timer expires at 50us 01: Timer expires at 10ms 10: Timer expires at 50ms 11: Timer disabled Reset to 01 0: All memory transactions from PCI-X to PCIe will be mapped to TC0 1: All memory transactions from PCI-X to PCIe will be mapped to Traffic Class defined in bit [29:27] of offset 40h. Reset to 0 Reset to 001
16
PCI Retry Counter Status
RWC
18:17
PCI Retry Counter Control
RW
19
PCI Discard Timer Disable
RW
20
PCI Discard Timer Short Duration
RW
22:21
Configuration Request Retry Timer Counter Value Control
RW
23
Delayed Transaction Order Control
RW
25:24
Completion Timer Counter Value Control
RW
26
Isochronous Traffic Support Enable
RW
29:27
30
Traffic Class Used For Isochronous Traffic Serial Link Interface Loopback Enable
RW
RW / RO
0: Normal mode 1: Enable serial link interface loopback mode (TX to RX) if TM0=LOW, TM1=HIGH, TM2=HIGH, MSK_IN=HIGH, REVRSB=HIGH. PCI transaction from PCI bus will loop back to PCI bus RO for forward bridge Reset to 0
Page 48 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
31
Function
Primary Configuration Access Lockout
Type
RO / RW
Description
0: PI7C9X130 configuration space can be accessed from both interfaces 1: PI7C9X130 configuration space can only be accessed from the secondary interface. Primary bus accessed receives completion with CRS status for forward bridge, or target retry for reverse bridge Reset to 0 if TM0 is LOW
7.4.33
RESERVED REGISTER - OFFSET 44h
Bit
31:0
Function
Reserved
Type
RO
Description
Reset to 00000000h
7.4.34
ARBITER ENABLE REGISTER - OFFSET 48h
Bit
0
Function
Enable Arbiter 0
Type
RW
Description
0: Disable arbitration for internal PI7C9X130 request 1: Enable arbitration for internal PI7C9X130 request Reset to 1 0: Disable arbitration for master 1 1: Enable arbitration for master 1 Reset to 1 0: Disable arbitration for master 2 1: Enable arbitration for master 2 Reset to 1 0: Disable arbitration for master 3 1: Enable arbitration for master 3 Reset to 1 0: Disable arbitration for master 4 1: Enable arbitration for master 4 Reset to 1 0: Disable arbitration for master 5 1: Enable arbitration for master 5 Reset to 1 0: Disable arbitration for master 6 1: Enable arbitration for master 6 Reset to 1 0: Disable arbitration for master 7 1: Enable arbitration for master 7 Reset to 1 0: Disable arbitration for master 8 1: Enable arbitration for master 8 Reset to 1
1
Enable Arbiter 1
RW
2
Enable Arbiter 2
RW
3
Enable Arbiter 3
RW
4
Enable Arbiter 4
RW
5
Enable Arbiter 5
RW
6
Enable Arbiter 6
RW
7
Enable Arbiter 7
RW
8
Enable Arbiter 8
RW
Page 49 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.35
ARBITER MODE REGISTER - OFFSET 48h
Bit
9
Function
External Arbiter Bit
Type
RO
Description
0: Enable internal arbiter (if CFN_L is tied LOW) 1: Use external arbiter (if CFN_L is tied HIGH) Reset to 0/1 according to what CFN_L is tied to 0: Broken master timeout disable 1: This bit enables the internal arbiter to count 16 PCI bus cycles while waiting for FRAME_L to become active when a device's PCI bus GNT is active and the PCI bus is idle. If the broken master timeout expires, the PCI bus GNT for the device is de-asserted. Reset to 0 0: A broken master will be ignored forever after de-asserting its REQ_L for at least 1 clock 1: Refresh broken master state after all the other masters have been served once Reset to 0 08h: These bits are the initialization value of a counter used by the internal arbiter. It controls the number of PCI bus cycles that the arbiter holds a device's PCI bus GNT active after detecting a PCI bus REQ_L from another device. The counter is reloaded whenever a new PCI bus GNT is asserted. For every new PCI bus GNT, the counter is armed to decrement when it detects the new fall of FRAME_L. If the arbiter fairness counter is set to 00h, the arbiter will not remove a device's PCI bus GNT until the device has de-asserted its PCI bus REQ. Reset to 08h 0: GNT_L not de-asserted after granted master assert FRAME_L 1: GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting FRAME_L Reset to 0 Reset to 0
10
Broken Master Timeout Enable
RW
11
Broken Master Refresh Enable
RW
19:12
Arbiter Fairness Counter
RW
20
GNT_L Output Toggling Enable
RW
21
Reserved
RO
7.4.36
ARBITER PRIORITY REGISTER - OFFSET 48h
Bit
22
Function
Arbiter Priority 0
Type
RW
Description
0: Low priority request to internal PI7C9X130 1: High priority request to internal PI7C9X130 Reset to 1 0: Low priority request to master 1 1: High priority request to master 1 Reset to 0 0: Low priority request to master 2 1: High priority request to master 2 Reset to 0 0: Low priority request to master 3 1: High priority request to master 3 Reset to 0 0: Low priority request to master 4 1: High priority request to master 4 Reset to 0
23
Arbiter Priority 1
RW
24
Arbiter Priority 2
RW
25
Arbiter Priority 3
RW
26
Arbiter Priority 4
RW
Page 50 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
27
Function
Arbiter Priority 5
Type
RW
Description
0: Low priority request to master 5 1: High priority request to master 5 Reset to 0 0: Low priority request to master 6 1: High priority request to master 6 Reset to 0 0: Low priority request to master 7 1: High priority request to master 7 Reset to 0 0: Low priority request to master 8 1: High priority request to master 8 Reset to 0 Reset to 0
28
Arbiter Priority 6
RW
29
Arbiter Priority 7
RW
30
Arbiter Priority 8
RW
31
Reserved
RO
7.4.37 7.4.38
RESERVED REGISTERS - OFFSET 4Ch TO 64h EXPRESS TRANSMITTER/RECEIVER CONTROL REGISTER - OFFSET 68h
Bit
1:0
Function
Nominal Driver Current Control
Type
RW
Description
00: 20mA 01: 10mA 10: 28mA 11: Reserved Reset to 00 0000: 1.00 x nominal driver current 0001: 1.05 x nominal driver current 0010: 1.10 x nominal driver current 0011: 1.15 x nominal driver current 0100: 1.20 x nominal driver current 0101: 1.25 x nominal driver current 0110: 1.30 x nominal driver current 0111: 1.35 x nominal driver current 1000: 1.60 x nominal driver current 1001: 1.65 x nominal driver current 1010: 1.70 x nominal driver current 1011: 1.75 x nominal driver current 1100: 1.80 x nominal driver current 1101: 1.85 x nominal driver current 1110: 1.90 x nominal driver current 1111: 1.95 x nominal driver current Reset to 0000
5:2
Driver Current Scale Multiple Control
RW
Page 51 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
11:8
Function
Driver De-emphasis Level Control
Type
RW
Description
0000: 0.00 db 0001: -0.35 db 0010: -0.72 db 0011: -1.11 db 0100: -1.51 db 0101: -1.94 db 0110: -2.38 db 0111: -2.85 db 1000: -3.35 db 1001: -3.88 db 1010: -4.44 db 1011: -5.04 db 1100: -5.68 db 1101: -6.38 db 1110: -7.13 db 1111: -7.96 db Reset to 1000 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset to 00 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset to 00 Reset to 00h
13:12
Transmitter Termination Control
RW
15:14
Receiver Termination Control
RW
29:16
Reserved
RO
7.4.39
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER - OFFSET 68h
Bit
31:30
Function
Memory Write Fragment Control
Type
RW
Description
Upstream Memory Write Fragment Control 00: Fragment at 32-byte boundary 01: Fragment at 64-byte boundary 1x: Fragement at 128-byte boundary Reset to 10h
7.4.40 7.4.41
RESERVED REGISTER - OFFSET 6Ch EEPROM AUTOLOAD CONTROL/STATUS REGISTER - OFFSET 70h
Bit
0
Function
Initiate EEPROM Read or Write Cycle
Type
RW
Description
This bit will be reset to 0 after the EEPROM operation is finished. 0: EEPROM AUTOLOAD disabled 0 -> 1: Starts the EEPROM Read or Write cycle Reset to 0
Page 52 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
1
Function
Control Command for EEPROM
Type
RW
Description
0: Read 1: Write Reset to 0 0: EEPROM acknowledge is always received during the EEPROM cycle 1: EEPROM acknowledge is not received during EEPROM cycle Reset to 0 0: EEPROM autoload is not successfully completed 1: EEPROM autoload is successfully completed Reset to 0 Where PCLK is 125MHz 00: PCLK / 4096 01: PCLK / 2048 10: PCLK / 1024 11: PCLK / 128 Reset to 00 0: Enable EEPROM autoload 1: Disable EEPROM autoload Reset to 0 0: Normal speed of EEPROM autoload 1: Increase EEPROM autoload by 32x Reset to 0 0: EEPROM autoload is not on going 1: EEPROM autoload is on going Reset to 0 EEPROM word address for EEPROM cycle Reset to 0000000 EEPROM data to be written into the EEPROM Reset to 0000h
2
EEPROM Error
RO
3
EPROM Autoload Complete Status
RO
5:4
EEPROM Clock Frequency Control
RW
6
EEPROM Autoload Control
RW
7
Fast EEPROM Autoload Control
RW
8
EEPROM Autoload Status
RO
15:9
EEPROM Word Address EEPROM Data
RW
31:16
RW
7.4.42
HOT SWAP CONTROL AND STATUS REGISTER - OFFSET 74h
Bit
7:0 15:8 16 17 18
Function
Capability ID for Hot Swap Next Capability Pointer Device Hiding Arm ENUM_L signal Mask Pending Insertion or Extraction
Type
RO RO RW RW RW
Description
Reset to 06h when Hot Sawp is enable (HS_EN=1) or 00h when Hot Swap is disabled (HS_EN=0) Reset to 00h to inidicate the end of the capability chain Device Hiding Armed when this bit is set to 1 Reset to 0 ENUM_L signal is masked when this bit is set to 1 Reset to 0 When this bit is 1, INS is armed, or either INS or EXT has a value of logic 1 When this bit is 0, INS is not armed or both INS and EXT have a value of logic 0 Reset to 0h When this bit is 1, LED is on When this bit is 0, LED is off Reset to 0 PI=01 supports PI=00 plus device hiding and pending insertion or extraction bits Reset to 01
19
LED On Off
RW
21:20
Programming Interface
RO
Page 53 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
22
Function
EXT for Extraction
Type
RWC
Description
EXT bit indicates ENUM_L status of extraction. When EXT is 1, ENUM_L is asserted Reset to 0 INS bit indicates ENUM_L status of insertion. When INS is 1, ENUM_L is asserted Reset to 1 Reset to 00h
23
INS for Insertion
RWC
31:24
Reserved
RO
7.4.43
GPIO DATA AND CONTROL REGISTER - OFFSET 78h
Bit
11:0 15:12 19:16 23:20 27:24 31:28
Function
Reserved GPIO Output Write1-to-Clear GPIO Output Write1-to-Set GPIO Output Enable Write-1-to-Clear GPIO Output Enable Write-1-to-Set GPIO Input Data Register
Type
RO RW RW RW RW RO
Description
Reset to 000h Reset to 0h Reset to 0h Reset to 0h Reset to 0h Reset to 0h
7.4.44 7.4.45
RESERVED REGISTER - OFFSET 7Ch PCI-X CAPABILITY ID REGISTER - OFFSET 80h
Bit
7:0
Function
PCI-X Capability ID
Type
RO
Description
PCI-X Capability ID Reset to 07h
7.4.46
NEXT CAPABILITY POINTER REGISTER - OFFSET 80h
Bit
15:8
Function
Next Capability Pointer
Type
RO
Description
Point to power management Reset to 90h
7.4.47
PCI-X SECONDARY STATUS REGISTER - OFFSET 80h
Bit
16
Function
64-bit Device on Secondary Bus Interface 133MHz Capable
Type
RO
Description
64-bit supported when DEV64 is set to high Reset to 1in forward bridge mode and DEV64 is set to high or reset to 0 in reverse bridge mode When this bit is 1, PI7C9X130 is 133MHz capable on its secondary bus interface
17
RO
Page 54 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
18
Function
Split Completion Discarded
Type
RO / RWC
Description
Reset to 1 in forward bridge mode or 0 in reverse bridge mode This bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode When this is set to 1, a split completion has been discarded by PI7C9X130 at secondary bus because the requester did not accept the split completion transaction Reset to 0 This bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode When this bit is set to 1, an unexpected split completion has been received with the requester ID equaled to the secondary bus number, device number, and function number at the PI7X9X130 secondary bus interface Reset to 0 When this bit is set to 1, a split completion has been terminated by PI7C9X130 with either a retry or disconnect at the next ADB due to the buffer full condition Reset to 0 When this bit is set to 1, a split request is delayed because PI7C9X130 is not able to forward the split request transaction to its secondary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register Reset to 0 These bits are only meaningful in forward bridge mode. In reverse bridge mode, all three bits are set to zero. 000: Conventional PCI mode (minimum clock period not applicable) 001: 66MHz (minimum clock period is 15ns) 010: 100 to 133MHz (minimum clock period is 7.5ns) 011: Reserved 1xx: Reserved Reset to 000 0000000
19
Unexpected Split Completion
RWC
20
Split Completion Overrun
RWC
21
Split Request Delayed
RWC
24:22
Secondary Clock Frequency
RO
31:25
Reserved
RO
7.4.48
PCI-X BRIDGE STATUS REGISTER - OFFSET 84h
Bit
2:0
Function
Function Number
Type
RO
Description
Function number (AD [10:8] of a type 0 configuration transaction) Reset to 000 Device number (AD [15:11] of a type 0 configuration transaction) is assigned to the PI7C9X130 by the connection of system hardware. Each time the PI7C9X130 is addressed by a configuration write transaction, the bridge updates this register with the contents of AD [15:11] of the address phase of the configuration transaction, regardless of which register in the PI7C9X130 is addressed by the transaction. The PI7C9X130 is addressed by a configuration write transaction if all of the following are true: * The transaction uses a configuration write command * IDSEL is asserted during the address phase * AD [1:0] are 00 (type o configuration transaction) * AD [10:8] of the configuration address contain the appropriate function number Reset to 11111
7:3
Device Number
RO
Page 55 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
15:8
Function
Bus Number
Type
RO
Description
Additional address from which the contents of the primary bus number register on type 1 configuration space header is read. The PI7C9X130 uses the bus number, device number, and function number fields to create a completer ID when responding with a split completion to a read of an internal PI7C9X130 register. These fields are also used for cases when one interface is in conventional PCI mode and the other is in PCI-X mode. Reset to 11111111 64-bit supported when DEV64 is set to high Reset to 0 in forward bridge mode or in reverse bridge mode with REQ64_L is high at the de-assertion of RESET_L or reset to 1 in reverse bridge mode with REQ64_L is low at the de-assertion of RESET_L When this bit is 1, PI7C9X130 is 133MHz capable on its primary bus interface Reset to 0 in forward bridge mode or 1 in reverse bridge mode This bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode When this is set to 1, a split completion has been discarded by PI7C9X130 at primary bus because the requester did not accept the split completion transaction Reset to 0 This bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode When this is set to 1, an unexpected split completion has been received with the requester ID equaled to the primary bus number, device number, and function number at the PI7X9X130 primary bus interface Reset to 0 When this bit is set to 1, a split completion has been terminated by PI7C9X130 with either a retry or disconnect at the next ADB due to the buffer full condition Reset to 0 When this bit is set to 1, a split request is delayed because PI7C9X130 is not able to forward the split request transaction to its primary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register Reset to 0 0000000000
16
64-bit Device on Primary Bus Interface
RO
17
133MHz Capable
RO
18
Split Completion Discarded
RO / RWC
19
Unexpected Split Completion
RWC
20
Split Completion Overrun
RWC
21
Split Request Delayed
RWC
31:22
Reserved
RO
7.4.49
UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h
Bit
15:0
Function
Upstream Split Transaction Capability
Type
RO
Description
Upstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the secondary bus in addressing the completers on the primary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h Upstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X130 is allowed to forward all split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h
31:16
Split Transaction Commitment Limit
RW
Page 56 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.50
DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch
Bit
15:0
Function
Downstream Split Transaction Capability
Type
RO
Description
Downstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the primary bus in addressing the completers on the secondary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h Downstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X130 is allowed to forward all split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h
31:16
Downstream Split Transaction Commitment Limit
RW
7.4.51
POWER MANAGEMENT ID REGISTER - OFFSET 90h
Bit
7:0
Function
Power Management ID
Type
RO
Description
Power Management ID Register Reset to 01h
7.4.52
NEXT CAPABILITY POINTER REGISTER - OFFSET 90h
Bit
15:8
Function
Next Pointer
Type
RO
Description
Next pointer (point to Subsystem ID and Subsystem Vendor ID) Reset to A8h
7.4.53
POWER MANAGEMENT CAPABILITY REGISTER - OFFSET 90h
Bit
18:16
Function
Version Number
Type
RO
Description
Version number that complies with revision 2.0 of the PCI Power Management Interface specification. Reset to 010 PME clock is not required for PME_L generation Reset to 0 Reset to 0 DSI - no special initialization of this function beyond the standard PCI configuration header is required following transition to the D0 un-initialized state Reset to 0
19
PME Clock
RO
20 21
Reserved Device Specific Initialization (DSI)
RO RO
Page 57 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
24:22
Function
AUX Current
Type
RO
Description
000: 0mA 001: 55mA 010: 100mA 011: 160mA 100: 220mA 101: 270mA 110: 320mA 111: 375mA Reset to 001 D1 power management is not supported Reset to 0 D2 power management is not supported Reset to 0 PME_L is supported in D3 cold, D3 hot, and D0 states. Reset to 11001
25
D1 Power Management D2 Power Management PME_L Support
RO
26
RO
31:27
RO
7.4.54
POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h
Bit
1:0
Function
Power State
Type
RW
Description
Power State is used to determine the current power state of PI7C9X130. If a non-implemented state is written to this register, PI7C9X130 will ignore the write data. When present state is D3 and changing to D0 state by programming this register, the power state change causes a device reset without activating the RESET_L of PCI/PCI-X bus interface 00: D0 state 01: D1 state not implemented 10: D2 state not implemented 11: D3 state Reset to 00 Reset to 000000 0: PME_L assertion is disabled 1: PME_L assertion is enabled Reset to 0 Data register is not implemented Reset to 0000 Data register is not implemented Reset to 00 PME_L is supported Reset to 0
7:2 8
Reserved PME Enable
RO RWS
12:9
Data Select
RO
14:13
Data Scale
RO
15
PME Status
RWCS
7.4.55
PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER - OFFSET 94h
Bit
21:16 22
Function
Reserved B2/B3 Support
Type
RO RO
Description
Reset to 000000 0: B2 / B3 not support for D3hot Reset to 0
Page 58 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
23
Function
PCI Bus Power/Clock Control Enable Data Register
Type
RO
Description
0: PCI Bus Power/Clock Disabled Reset to 0 Data register is not implemented Reset to 00h
31:24
RO
7.4.56 7.4.57
RESERVED REGISTERS - OFFSET 98h TO 9Ch CAPABILITY ID REGISTER - OFFSET A0h
Bit
7:0
Function
Capability ID
Type
RO
Description
Capability ID for Slot Identification. SI is off by default but can be turned on through EEPROM interface Reset to 04h
7.4.58
NEXT POINTER REGISTER - OFFSET A0h
Bit
15:8
Function
Next Pointer
Type
RO
Description
Next pointer - points to PCI Express capabilities register Reset to B0h
7.4.59
SLOT NUMBER REGISTER - OFFSET A0h
Bit
20:16
Function
Expansion Slot Number First In Chassis
Type
RW
Description
Expansion slot number Reset to 00000 First in chassis Reset to 0 Reset to 00
21
RW
23:22
Reserved
RO
7.4.60
CHASSIS NUMBER REGISTER - OFFSET A0h
Bit
31:24
Function
Chassis Number
Type
RW
Description
Chassis number Reset to 00h
Page 59 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.61
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER - OFFSET A4h
Bit
1:0
Function
CLKOUT0 Enable
Type
RW
Description
CLKOUT (Slot 0) Enable for forward bridge mode only 00: enable CLKOUT0 01: enable CLKOUT0 10: enable CLKOUT0 11: disable CLKOUT0 and driven LOW Reset to 00 CLKOUT (Slot 1) Enable for forward bridge mode only 00: enable CLKOUT1 01: enable CLKOUT1 10: enable CLKOUT1 11: disable CLKOUT1 and driven LOW Reset to 00 CLKOUT (Slot 2) Enable for forward bridge mode only 00: enable CLKOUT2 01: enable CLKOUT2 10: enable CLKOUT2 11: disable CLKOUT2 and driven LOW Reset to 00 CLKOUT (Slot 3) Enable for forward bridge mode only 00: enable CLKOUT3 01: enable CLKOUT3 10: enable CLKOUT3 11: disable CLKOUT3 and driven LOW Reset to 00 CLKOUT (Device 1) Enable for forward bridge mode only 0: enable CLKOUT4 1: disable CLKOUT4 and driven LOW Reset to 0 CLKOUT (Device 2) Enable for forward bridge mode only 0: enable CLKOUT5 1: disable CLKOUT5 and driven LOW Reset to 0 CLKOUT (the bridge) Enable for forward bridge mode only 0: enable CLKOUT6 1: disable CLKOUT6 and driven LOW Reset to 0 Reset to 0 Reset to 0 Secondary clock stop status 0: secondary clock not stopped 1: secondary clock stopped Reset to 0
3:2
CLKOUT1 Enable
RW
5:4
CLKOUT2 Enable
RW
7:6
CLKOUT3 Enable
RW
8
CLKOUT4 Enable
RW
9
CLKOUT5 Enable
RW
10
CLKOUT6 Enable
RW
11 12 13
Reserved Reserved Secondary Clock Stop Status
RO RO RO
Page 60 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
14
Function
Secondary Clkrun Protocol Enable
Type
RW
Description
0: disable protocol 1: enable protocol Reset to 0 0: Stop the secondary clock only when bridge is at D3hot state 1: Stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus Reset to 0 Reset to 0000h
15
Clkrun Mode
RW
31:16
Reserved
RO
7.4.62
CAPABILITY ID REGISTER - OFFSET A8h
Bit
7:0
Function
Capability ID
Type
RO
Description
Capability ID for subsystem ID and subsystem vendor ID Reset to 0Dh
7.4.63
NEXT POINTER REGISTER - OFFSET A8h
Bit
15:8
Function
Next Item Pointer
Type
RO
Description
Next item pointer (point to PCI Express Capability by default but can be programmed to A0h if Slot Identification Capability is enabled) Reset to B0h
7.4.64
RESERVED REGISTER - OFFSET A8h
Bit
31:16
Function
Reserved
Type
RO
Description
Reset to 0000h
7.4.65
SUBSYSTEM VENDOR ID REGISTER - OFFSET ACh
Bit
15:0
Function
Subsystem Vendor ID
Type
RO
Description
Subsystem vendor ID identifies the particular add-in card or subsystem Reset to 00h
7.4.66
SUBSYSTEM ID REGISTER - OFFSET ACh
Bit
31:16
Function
Subsystem ID
Type
RO
Description
Subsystem ID identifies the particular add-in card or subsystem Reset to 00h
7.4.67
PCI EXPRESS CAPABILITY ID REGISTER - OFFSET B0h
Bit Function Type Description
Page 61 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
7:0
Function
PCI Express Capability ID
Type
RO
Description
PCI Express capability ID Reset to 10h
7.4.68
NEXT CAPABILITY POINTER REGISTER - OFFSET B0h
Bit
15:8
Function
Next Item Pointer
Type
RO
Description
Next item pointer (points to VPD register) Reset to D8h
7.4.69
PCI EXPRESS CAPABILITY REGISTER - OFFSET B0h
Bit
19:16 23:20
Function
Capability Version Device / Port Type
Type
RO RO
Description
Reset to 1h 0000: PCI Express endpoint device 0001: Legacy PCI Express endpoint device 0100: Root port of PCI Express root complex 0101: Upstream port of PCI Express switch 0110: Downstream port of PCI Express switch 0111: PCI Express to PCI bridge 1000: PCI to PCI Express bridge Others: Reserved Reset to 7h for Forward Bridge or 8h for Reverse Bridge Reset to 0 for Forward Bridge or 1 for Reverse Bridge Reset to 0h Reset to 0
24 29:25 31:30
Slot Implemented Interrupt Message Number Reserved
RO RO RO
7.4.70
DEVICE CAPABILITY REGISTER - OFFSET B4h
Bit
2:0
Function
Maximum Payload Size
Type
RO
Description
000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 001 No phantom functions supported Reset to 0 8-bit tag field supported Reset to 1h
4:3
Phantom Functions
RO
5
8-bit Tag Field
RO
Page 62 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
8:6
Function
Endpoint L0's Latency
Type
RO
Description
Endpoint L0's acceptable latency 000: less than 64 ns 001: 64 - 128 ns 010: 128 - 256 ns 011: 256 - 512 ns 100: 512 ns - 1 us 101: 1 - 2 us 110: 2 - 4 us 111: more than 4 us Reset to 000 Endpoint L1's acceptable latency 000: less than 1 us 001: 1 - 2 us 010: 2 - 4 us 011: 4 - 8 us 100: 8 - 16 us 101: 16 - 32 us 110: 32 - 64 us 111: more than 64 us Reset to 000 0: If Hot Plug is disabled 1: If Hot Plug is enabled at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enable at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enable at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 000 These bits are set by the Set_Slot_Power_Limit message Reset to 00h This value is set by the Set_Slot_Power_Limit message Reset to 00 Reset to 0h
11:9
Endpoint L1's Latency
RO
12
Attention Button Present
RO
13
Attention Indicator Present
RO
14
Power Indicator Present
RO
17:15 25:18
Reserved Captured Slot Power Limit Value Captured Slot Power Limit Scale Reserved
RO RO
27:26
RO
31:28
RO
7.4.71
DEVICE CONTROL REGISTER - OFFSET B8h
Bit
0 1 2 3
Function
Correctable Error Reporting Enable Non-Fatal Error Reporting Enable Fatal Error Reporting Enable Unsupported Request Reporting Enable Relaxed Ordering Enable
Type
RW RW RW RW
Description
Reset to 0h Reset to 0h Reset to 0h Reset to 0h
4
RO
Relaxed Ordering disabled Reset to 0h
Page 63 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
7:5
Function
Max Payload Size
Type
RW
Description
This field sets the maximum TLP payload size for the PI7C9X130 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 000 Reset to 0 Phantom functions not supported Reset to 0 Auxiliary power PM not supported Reset to 0 Bridge never sets the No Snoop attribute in the transaction it initiates Reset to 0 This field sets the maximum Read Request Size for the device as a requester 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 2h Reset to 0
8 9
Extended Tag Field Enable Phantom Functions Enable Auxiliary Power PM Enable No Snoop Enable
RW RO
10
RO
11
RO
14:12
Maximum Read Request Size
RW
15
Configuration Retry Enable
RW
7.4.72
DEVICE STATUS REGISTER - OFFSET B8h
Bit
16 17 18 19 20 21
Function
Correctable Error Detected Non-Fatal Error Detected Fatal Error Detected Unsupported Request Detected AUX Power Detected Transaction Pending
Type
RWC RWC RWC RWC RO RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1 0: No transaction is pending on transaction layer interface 1: Transaction is pending on transaction layer interface Reset to 0 Reset to 0000000000
31:22
Reserved
RO
Page 64 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.73
LINK CAPABILITY REGISTER - OFFSET BCh
Bit
3:0
Function
Maximum Link Speed
Type
RO
Description
Indicates the maximum speed of the Express link 0001: 2.5Gb/s link Reset to 1h Indicates the maximum width of the Express link (x4 at reset) 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 Reset to 000100 This field indicates the level of Active State Power Management Support 00: reserved 01: L0's entry supported 10: reserved 11: L0's and L1's supported Reset to 11 Reset to 3h Reset to 0h Reset to 0h Reset to 00h
9:4
Maximum Link Width
RO
11:10
ASPM Support
RO
14:12 17:15 23:18 31:24
L0's Exit Latency L1's Exit Latency Reserved Port Number
RO RO RO RO
7.4.74
LINK CONTROL REGISTER - OFFSET C0h
Bit
1:0
Function
ASPM Control
Type
RW
Description
This field controls the level of ASPM supported on the Express link 00: disabled 01: L0's entry enabled 10: L1's entry enabled 11: L0's and L1's entry enabled Reset to 00 Reset to 0 Read completion boundary not supported Reset to 0 RO for Forward Bridge Reset to 0 RO for Forward Bridge Reset to 0 Reset to 0 Reset to 0 Reset to 00h
2 3
Reserved Read Completion Boundary (RCB) Link Disable
RO RO
4
RO / RW
5
Retrain Link
RO / RW
6 7 15:8
Common Clock Configuration Extended Sync Reserved
RW RW RO
Page 65 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.75
LINK STATUS REGISTER - OFFSET C0h
Bit
19:16
Function
Link Speed
Type
RO
Description
This field indicates the negotiated speed of the Express link 001: 2.5Gb/s link Reset to 1h 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 Reset to 000100 Reset to 0 Reset to 0 Reset to 1 Reset to 0
25:20
Negotiated Link Width
RO
26 27 28 31:29
Link Train Error Link Training Slot Clock Configuration Reserved
RO RO RO RO
7.4.76
SLOT CAPABILITY REGISTER - OFFSET C4h
Bit
0
Function
Attention Button Present
Type
RO
Description
0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 0 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 0 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 00h Reset to 00 Reset to 00 Reset to 0
1 2
Power Controller Present MRL Sensor Present
RO RO
3
Attention Indicator Present
RO
4
Power Indicator Present
RO
5 6
Hot Plug Surprise Hot Plug Capable
RO RO
14:7 16:15 18:17 31:19
Slot Power Limit Value Slot Power Limit Scale Reserved Physical Slot Number
RO RO RO RO
Page 66 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.77
SLOT CONTROL REGISTER - OFFSET C8h
Bit
0 1 2 3 4
Function
Attention Button Present Enable Power Fault Detected Enable MRL Sensor Changed Enable Presence Detect Changed Enable Command Completed Interrupt Enable Hot Plug Interrupt Enable Attention Indicator Control Power Indicator Control Power Controller Control Reserved
Type
RW RW RW RW RW
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
5 7:6 9:8 10 15:11
RW RW RW RW RO
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.78
SLOT STATUS REGISTER - OFFSET C8h
Bit
16 17 18 19 20 21 22 31:23
Function
Attention Button Pressed Power Fault Detected MRL Sensor Changed Presence Detect Changed Command Completed MRL Sensor State Presence Detect State Reserved
Type
RO RO RO RO RO RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.79
XPIP CONFIGURATION REGISTER 0 - OFFSET CCh
Bit
0 1 2 3
Function
Hot Reset Enable Loopback Function Enable Cross Link Function Enable Software Direct to Configuration State when in LTSSM state Internal Selection for Debug Mode
Type
RW RW RW RW
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
4
RW
Reset to 0
Page 67 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
7:5 12:8 15:13 31:16
Function
Negotiate Lane Number of Times TS1 Number Counter Reserved LTSSM Enter L1 Timer Default Value
Type
RW RW RO RW
Description
Reset to 3h Reset to 10h Reset to 0 Reset to 0400h
7.4.80
XPIP CONFIGURATION REGISTER 1 - OFFSET D0h
Bit
9:0 15:10 31:16
Function
L0's Lifetime Timer Reserved L1 Lifetime Timer
Type
RW RO RW
Description
Reset to 0 Reset to 0 Reset to 0
7.4.81
XPIP CONFIGURATION REGISTER 2 - OFFSET D4h
Bit
7:0
Function
CDR Recovery Time (in the number of FTS order sets) L0's Exit to L0 Latency Reserved L1 Exit to L0 Latency Reserved
Type
RW
Description
Reset to 54h A Fast Training Sequence order set composes of one K28.5 (COM) Symbol and three K28.1 Symbols. Reset to 2h Reset to 0 Reset to 19h Reset to 0
14:8 15 22:16 23
RW RO RW RO
7.4.82
HOT SWAP SWITCH DEBOUNCE COUNTER - OFFSET D4h
Bit
31:24
Function
Hot Swap Debounce Counter
Type
RO / RW
Description
If Hot Swap is enabled, this counter is read-writeable (RW). This counter is read only (RO) if Hot Swap is disabled 00h: 1ms 01h: 2ms 02h: 3ms 03h: 4ms ... FFh: 256ms Reset to 0
7.4.83
CAPABILITY ID REGISTER - OFFSET D8h
Bit
7:0
Function
Capability ID for VPD Register
Type
RO
Description
Reset to 03h
Page 68 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.84
NEXT POINTER REGISTER - OFFSET D8h
Bit
15:8
Function
Next Pointer
Type
RO
Description
Next pointer (F0h, points to MSI capabilities) Reset to F0h
7.4.85
VPD REGISTER - OFFSET D8h
Bit
17:16 23:18 30:24 31
Function
Reserved VPD Address for Read/Write Cycle Reserved VPD Operation
Type
RO RW RO RW
Description
Reset to 0 Reset to 0 Reset to 0 0: Generate a read cycle from the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at `0' until EEPROM cycle is finished, after which the bit is then set to `1'. Data for reads is available at register ECh. 1: Generate a write cycle to the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at `1' until EEPROM cycle is finished, after which it is then cleared to `0'. Reset to 0
7.4.86
VPD DATA REGISTER - OFFSET DCh
Bit
31:0
Function
VPD Data
Type
RW
Description
VPD Data (EEPROM data [address + 0x40]) The least significant byte of this register corresponds to the byte of VPD at the address specified by the VPD address register. The data read form or written to this register uses the normal PCI byte transfer capabilities. Reset to 0
7.4.87 7.4.88
RESERVED REGISTER - OFFSET E0h TO ECh MESSAGE SIGNALED INTERRUPTS ID REGISTER - OFFSET F0h
Bit
7:0
Function
Capability ID for MSI Registers
Type
RO
Description
Reset to 05h
7.4.89
NEXT CAPABILITIES POINTER REGISTER - OFFSET F0h
Bit
15:8
Function
Next Pointer
Type
RO
Description
Next pointer (00h indicates the end of capabilities) Reset to 00h
Page 69 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.90
MESSAGE CONTROL REGISTER - OFFSET F0h
Bit
16 19:17
Function
MSI Enable Multiple Message Capable
Type
RW RO
Description
0: Disable MSI and default to INTx for interrupt 1: Enable MSI for interrupt service and ignore INTx interrupt pins 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000 Reset to 1 Reset to 00h
22:20
Multiple Message Enable
RW
23 31:24
64-bit Address Capable Reserved
RW RO
7.4.91
MESSAGE ADDRESS REGISTER - OFFSET F4h
Bit
1:0 31:2
Function
Reserved System Specified Message Address
Type
RO RW
Description
Reset to 00 Reset to 0
7.4.92
MESSAGE UPPER ADDRESS REGISTER - OFFSET F8h
Bit
31:0
Function
System Specified Message Upper Address
Type
RW
Description
Reset to 0
7.4.93
MESSAGE DATA REGISTER - OFFSET FCh
Bit
15:0 31:16
Function
System Specified Message Data Reserved
Type
RW RO
Description
Reset to 0 Reset to 0
Page 70 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.94
ADVANCE ERROR REPORTING CAPABILITY ID REGISTER - OFFSET 100h
Bit
15:0
Function
Advance Error Reporting Capability ID
Type
RO
Description
Reset to 0001h
7.4.95
ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER - OFFSET 100h
Bit
19:16
Function
Advance Error Reporting Capability Version
Type
RO
Description
Reset to 1h
7.4.96
NEXT CAPABILITY OFFSET REGISTER - OFFSET 100h
Bit
31:20
Function
Next Capability Offset
Type
RO
Description
Next capability offset (150h points to VC capability) Reset to 150h
7.4.97
UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 104h
Bit
0 3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21
Function
Training Error Status Reserved Data Link Protocol Error Status Reserved Poisoned TLP Status Flow Control Protocol Error Status Completion Timeout Status Completer Abort Status Unexpected Completion Status Receiver Overflow Status Malformed TLP Status ECRC Error Status Unsupported Request Error Status Reserved
Type
RWCS RO RWCS RO RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.98
UNCORRECTABLE ERROR MASK REGISTER - OFFSET 108h
Bit
0
Function
Training Error Mast
Type
RWS
Description
Reset to 0
Page 71 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21
Function
Reserved Data Link Protocol Error Mask Reserved Poisoned TLP Mask Flow Control Protocol Error Mask Completion Timeout Mask Completion Abort Mask Unexpected Completion Mask Receiver Overflow Mask Malformed TLP Mask ECRC Error Mask Unsupported Request Error Mask Reserved
Type
RO RWS RO RWS RWS RWS RWS RWS RWS RWS RWS RWS RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.99
UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 10Ch
Bit
0 3:1 4 11:5 12 13
Function
Training Error Severity Reserved Data Link Protocol Error Severity Reserved Poisoned TLP Severity Flow Control Protocol Error Severity Completion Timeout Severity Completer Abort Severity Unexpected Completion Severity Receiver Overflow Severity Malformed TLP Severity ECRC Error Severity Unsupported Request Error Severity Reserved
Type
RWS RO RWS RO RWS RWS
Description
Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0 Reset to 1
14 15 16 17 18 19 20
RWS RWS RWS RWS RWS RWS RWS
Reset to 0 Reset to 0 Reset to 0 Reset to 1 Reset to 1 Reset to 0 Reset to 0
31:21
RO
Reset to 0
7.4.100 CORRECTABLE ERROR STATUS REGISTER - OFFSET 110h
Bit
0 5:1
Function
Receiver Error Status Reserved
Type
RWCS RO
Description
Reset to 0 Reset to 0
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Bit
6 7 8 11:9 12 13 31:14
Function
Bad TLP Status Bad DLLP Status REPLAY_NUM Rollover Status Reserved Replay Timer Timeout Status Advisory Non-Fatal Error Status Reserved
Type
RWCS RWCS RWCS RO RWCS RWCS RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.101 CORRECTABLE ERROR MASK REGISTER - OFFSET 114h
Bit
0 5:1 6 7 8 11:9 12 31:13
Function
Receiver Error Mask Reserved Bad TLP Mask Bad DLLP Mask REPLAY_NUM Rollover Mask Reserved Replay Timer Timeout Mask Reserved
Type
RWS RO RWS RWS RWS RO RWS RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.102 ADVANCED ERROR CAPABILITIES & CONTROL REGISTER - OFFSET 118h
Bit
4:0 5 6 7 8 31:9
Function
First Error Pointer ECRC Generation Capable ECRC Generation Enable ECRC Check Capable ECRC Check Enable Reserved
Type
ROS RO RWS RO RWS RO
Description
Reset to 0h Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.4.103 HEADER LOG REGISTER 1 - OFFSET 11Ch
Bit
7:0 15:8 23:16 31:24
Function
Header Byte 3 Header Byte 2 Header Byte 1 Header Byte 0
Type
ROS ROS ROS ROS
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.104 HEADER LOG REGISTER 2 - OFFSET 120h
Bit
7:0 15:8 23:16 31:24
Function
Header Byte 7 Header Byte 6 Header Byte 5 Header Byte 4
Type
ROS ROS ROS ROS
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
Page 73 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.105 HEADER LOG REGISTER 3 - OFFSET 124h
Bit
7:0 15:8 23:16 31:24
Function
Header Byte 11 Header Byte 10 Header Byte 9 Header Byte 8
Type
ROS ROS ROS ROS
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.106 HEADER LOG REGISTER 4 - OFFSET 128h
Bit
7:0 15:8 23:16 31:24
Function
Header Byte 15 Header Byte 14 Header Byte 13 Header Byte 12
Type
ROS ROS ROS ROS
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.107 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 12Ch
Bit
0
Function
Target Abort on Split Completion Status Master Abort on Split Completion Status Received Target Abort Status Received Master Abort Status Reserved Unexpected Split Completion Error Status Uncorrectable Split Completion Message Data Error Status Uncorrectable Data Error Status Uncorrectable Attribute Error Status Uncorrectable Address Error Status Delayed Transaction Discard Timer Expired Status PERR_L Assertion Detected Status SERR_L Assertion Detected Status Internal Bridge Error Status Reserved
Type
RWCS
Description
Reset to 0
1
RWCS
Reset to 0
2 3 4 5
RWCS RWCS RO RWCS
Reset to 0 Reset to 0 Reset to 0 Reset to 0
6
RWCS
Reset to 0
7 8
RWCS RWCS
Reset to 0 Reset to 0
9 10
RWCS RWCS
Reset to 0 Reset to 0
11 12 13 31:14
RWCS RWCS RWCS RO
Reset to 0 Reset to 0 Reset to 0 Reset to 0
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PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.108 SECONDARY UNCORRECTABLE ERROR MASK REGISTER - OFFSET 130h
Bit
0
Function
Target Abort on Split Completion Mask Master Abort on Split Completion Mask Received Target Abort Mask Received Master Abort Mask Reserved Unexpected Split Completion Error Mask Uncorrectable Split Completion Message Data Error Mask Uncorrectable Data Error Mask Uncorrectable Attribute Error Mask Uncorrectable Address Error Mask Delayed Transaction Discard Timer Expired Mask PERR_L Assertion Detected Mask SERR_L Assertion Detected Mask Internal Bridge Error Mask Reserved
Type
RWS
Description
Reset to 0
1
RWS
Reset to 0
2 3 4 5
RWS RWS RO RWS
Reset to 0 Reset to 1 Reset to 0 Reset to 1
6
RWS
Reset to 0
7 8 9 10
RWS RWS RWS RWS
Reset to 1 Reset to 1 Reset to 1 Reset to 1
11 12 13 31:14
RWS RWS RWS RO
Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.4.109 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 134h
Bit
0
Function
Target Abort on Split Completion Severity Master Abort on Split Completion Severity Received Target Abort Severity Received Master Abort Severity Reserved Unexpected Split Completion Error Severity Uncorrectable Split Completion Message Data Error Severity Uncorrectable Data Error Severity
Type
RWS
Description
Reset to 0
1
RWS
Reset to 0
2 3 4 5
RWS RWS RO RWS
Reset to 0 Reset to 0 Reset to 0 Reset to 0
6
RWS
Reset to 1
7
RWS
Reset to 0
Page 75 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Bit
8
Function
Uncorrectable Attribute Error Severity Uncorrectable Address Error Severity Delayed Transaction Discard Timer Expired Severity PERR_L Assertion Detected Severity SERR_L Assertion Detected Severity Internal Bridge Error Severity Reserved
Type
RWS
Description
Reset to 1
9
RWS
Reset to 1
10
RWS
Reset to 0
11 12 13 31:14
RWS RWS RWS RO
Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.4.110 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER - OFFSET 138h
Bit
4:0 31:5
Function
Secondary First Error Pointer Reserved
Type
ROW RO
Description
Reset to 0 Reset to 0
7.4.111 SECONDARY HEADER LOG REGISTER - OFFSET 13Ch - 148h
Bit
35:0
Function
Transaction Attribute Transaction Command Lower Transaction Command Upper
Type
ROS
Description
Transaction attribute, CBE [3:0] and AD [31:0] during attribute phase Reset to 0 Transaction command lower, CBE [3:0] during first address phase Reset to 0 Transaction command upper, CBE [3:0] during second address phase of DAC transaction Reset to 0 Reset to 0 Transaction address, AD [31:0] during first address phase Reset to 0 Transaction address, AD [31:0] during second address phase of DAC transaction Reset to 0
39:36
ROS
43:40
ROS
63:44 95:64
Reserved Transaction Address
ROS ROS
127:96
Transaction Address
ROS
7.4.112 RESERVED REGISTER - OFFSET 14Ch 7.4.113 VC CAPABILITY ID REGISTER - OFFSET 150h
Bit
15:0
Function
VC Capability ID
Type
RO
Description
Reset to 0002h
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PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.114 VC CAPABILITY VERSION REGISTER - OFFSET 150h
Bit
19:16
Function
VC Capability Version
Type
RO
Description
Reset to 1h
7.4.115 NEXT CAPABILITY OFFSET REGISTER - OFFSET 150h
Bit
31:20
Function
Next Capability Offset
Type
RO
Description
Next capability offset - the end of capabilities Reset to 0
7.4.116 PORT VC CAPABILITY REGISTER 1 - OFFSET 154h
Bit
2:0 3 6:4 7 9:8 11:10 31:12
Function
Extended VC Count Reserved Low Priority Extended VC Count Reserved Reference Clock Port Arbitration Table Entry Size Reserved
Type
RO RO RO RO RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.4.117 PORT VC CAPABILITY REGISTER 2 - OFFSET 158h
Bit
7:0 23:8 31:24
Function
VC Arbitration Capability Reserved VC Arbitration Table Offset
Type
RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0
7.4.118 PORT VC CONTROL REGISTER - OFFSET 15Ch
Bit
0 3:1 15:4
Function
Load VC Arbitration Table VC Arbitration Select Reserved
Type
RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0
7.4.119 PORT VC STATUS REGISTER - OFFSET 15Ch
Bit
16 31:17
Function
VC Arbitration Table Status Reserved
Type
RO RO
Description
Reset to 0 Reset to 0
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PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.4.120 VC0 RESOURCE CAPBILITY REGISTER - OFFSET 160h
Bit
7:0 13:8 14 15 22:16 23 31:24
Function
Port Arbitration Capability Reserved Advanced Packet Switching Reject Snoop Transactions Maximum Time Slots Reserved Port Arbitration Table Offset
Type
RO RO RO RO RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to0 Reset to 0 Reset to 0 Reset to 0
7.4.121 VC0 RESOURCE CONTROL REGISTER - OFFSET 164h
Bit
7:0 7:1 15:8 16 19:17 23:20 26:24 30:27 31
Function
TC / VC Map TC / VC Map Reserved Load Port Arbitration Table Port Arbitration Select Reserved VC ID Reserved VC Enable
Type
RO RW RO RO RO RO RO RO RO
Description
Reset to 1 Reset to 7Fh Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1
7.4.122 VC0 RESOURCE STATUS REGISTER - OFFSET 168h
Bit
0 1 31:2
Function
Port Arbitration Table 1 VC0 Negotiation Pending Reserved
Type
RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0
7.4.123 RESERVED REGISTERS - OFFSET 16Ch TO 2FCh 7.4.124 EXTENDED GPIO DATA AND CONTROL REGISTER - OFFSET 300h
Bit
2:0 5:3 8:6
Function
Extended GPIO output Extended GPIO output Extended GPIO output enable
Type
RWC RWS RWC
Description
GPIO [6:4] as output, write 1 to clear Reset to 0 GPIO [6:4] as output, write 1 to set Reset to 0 GPIO [6:4] enable, write 1 to clear Reset to 0
Page 78 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
11:9 14:12 31:16
Function
Extended GPIO output enable Extended GPIO input Reserved
Type
RWS RO RO
Description
GPIO [6:4] enable, write 1 to set Reset to 0 GPIO [6:4] as input Reset to 0 Reset to 0
7.4.125 EXTRA GPI/GPO DATA AND CONTROL REGISTER - OFFSET 304h
Bit
3:0 7:4 11:8 15:12 19:16 31:20
Function
Extra GPO Extra GPO Extra GPO enable Extra GPO enable Extra GPI Reserved
Type
RWC RWS RWC RWS RO RO
Description
GPO [3:0], write 1 to clear Reset to 0 GPO [3:0], write 1 to set Reset to 0 GPO [3:0] enable, write 1 to clear Reset to 0 GPO [3:0] enable, write 1 to set Reset to 0 Extra GPI [3:0] Data Register Reset to 0 Reset to 0
7.4.126 RESERVED REGISTERS - OFFSET 308h TO 30Ch 7.4.127 REPLAY AND ACKNOWLEDGE LATENCY TIMERS - OFFSET 310h
Bit
11:0 12 15:13 29:16 30
Function
Replay Timer Replay Timer Enable Reserved Acknowledge Latency Timer Acknowledge Latency Timer Enable Reserved
Type
RW RW RO RW RO
Description
Replay Timer Reset to 0 Replay Timer Enable Reset to 0 Reset to 0 Acknowledge Latency Timer Reset to 0 Acknowledge Latency Timer Enable Reset to 0 Reset to 0
31
RO
7.4.128 RESERVED REGISTERS - OFFSET 314h TO FFCh
Page 79 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.5
PCI CONFIGURATION REGISTERS FOR NON-TRANSPARENT BRIDGE MODE
The following section describes the configuration space when the device is in non-transparent bridge mode. The descriptions for different register type are listed as follow:
Register Type
RO ROS RW RWC RWS RWCS
Descriptions
Read Only Read Only and Sticky Read/Write Read/Write "1" to clear Read/Write and Sticky Read/Write "1" to clear and Sticky
7.5.1
VENDOR ID - OFFSET 00h
Bit
15:0
Function
Vendor ID
Type
RO
Description
Identifies Pericom as the vendor of this device. Returns 12D8h when read.
7.5.1
DEVICE ID - OFFSET 00h
Bit
31:16
Function
Device ID
Type
RO
Description
Identifies this device as the PI7C9X130. Returns E130 when read.
7.5.2
PRIMARY COMMAND REGISTER - OFFSET 04h
Bit
0
Function
I/O Space Enable
Type
RW
Description
0: Ignore I/O transactions on the primary interface 1: Enable response to memory transactions on the primary interface Reset to 0 0: Ignore memory read transactions on the primary interface 1: Enable memory read transactions on the primary interface Reset to 0 0: Do not initiate memory or I/O transactions on the primary interface and disable response to memory and I/O transactions on the secondary interface 1: Enable the PI7C9X130 to operate as a master on the primary interfaces for memory and I/O transactions forwarded from the secondary interface. If the primary of the reverse bridge is PCI-X mode, the PI7C9X130 is allowed to initiate a split completion transaction regardless of the status bit. Reset to 0 0: Bridge does not respond as a target to Special Cycle transactions, so this bit is defined as Read-Only and must return 0 when read Reset to 0 0: PI7C9X130 does not originate a Memory Write and Invalidate transaction. Implements this bit as Read-Only and returns 0 when read (unless forwarding a transaction for another master). This bit will be ignored in PCI-X mode. Reset to 0
1
Memory Space Enable
RW
2
Bus Master Enable
RW
3
Special Cycle Enable
RO
4
Memory Write and Invalidate Enable
RO
Page 80 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
5
Function
VGA Palette Snoop Enable Parity Error Response Enable
Type
RO
Description
0: Ignore VGA palette snoop access on the primary Reset to 0 0: May ignore any parity error that is detected and take its normal action 1: This bit if set, enables the setting of Master Data Parity Error bit in the Status Register when poisoned TLP received or parity error is detected and takes its normal action Reset to 0 Wait cycle control not supported Reset to 0 0: Disable 1: Enable PI7C9X130 in forward bridge mode to report non-fatal or fatal error message to the Root Complex. Also, in reverse bridge mode to assert SERR_L on the primary interface Reset to 0 Fast back-to-back enable not supported Reset to 0 0: INTx interrupt messages can be generated 1: Prevent INTx messages to be generated and any asserted INTx interrupts will be released. Reset to 0 Reset to 00000
6
RW
7
Wait Cycle Control
RO
8
Primary SERR_L Enable Bit
RW
9
Fast Back-to-Back Enable Primary Interrupt Disable
RO
10
RO / RW
15:11
Reserved
RO
7.5.3
PRIMARY STATUS REGISTER - OFFSET 04h
Bit
18:16 19
Function
Reserved Primary Interrupt Status
Type
RO RO
Description
Reset to 000 0: No INTx interrupt message request pending in PI7C9X130 primary 1: INTx interrupt message request pending in PI7C9X130 primary Reset to 0 1: PI7C9X130 supports the capability list (offset 34h in the pointer to the data structure) Reset to 1 This bit applies to reverse bridge only. 1: 66MHz capable Reset to 0 when forward bridge or 1 when reverse bridge. Reset to 0 This bit applies to reverse bridge only. 1: Enable fast back-to-back transactions Reset to 0 when forward bridge or 1 when reverse bridge with primary bus in PCI mode
20
Capability List Capable
RO
21
66MHz Capable
RO
22 23
Reserved Fast Back-to-Back Capable
RO RO
Page 81 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
24
Function
Master Data Parity Error Detected
Type
RWC
Description
Bit set if its Parity Error Enable bit is set and either of the conditions occurs on the primary: FORWARD BRIDGE - * Receives a completion marked poisoned * Poisons a write request REVERSE BRIDGE - * Detected parity error when receiving data or Split Response for read * Observes P_PERR_L asserted when sending data or receiving Split Response for write * Receives a Split Completion Message indicating data parity error occurred for non-posted write Reset to 0 These bits apply to reverse bridge only. 00: fast DEVSEL_L decoding 01: medium DEVSEL_L decoding 10: slow DEVSEL_L decoding 11: reserved Reset to 00 when forward bridge or 01 when reverse bridge. FORWARD BRIDGE - This bit is set when PI7C9X130 completes a request using completer abort status on the primary REVERSE BRIDGE - This bit is set to indicate a target abort on the primary Reset to 0 FORWARD BRIDGE - This bit is set when bridge receives a completion with completer abort completion status on the primary REVERSE BRIDGE - This bit is set when PI7C9X130 detects a target abort on the primary Reset to 0 FORWARD BRIDGE - This bit is set when PI7C9X130 receives a completion with unsupported request completion status on the primary REVERSE BRIDGE - This bit is set when PI7C9X130 detects a master abort on the primary FORWARD BRIDGE - This bit is set when PI7C9X130 sends an ERR_FATAL or ERR_NON_FATAL message on the primary REVERSE BRIDGE - This bit is set when PI7C9X130 asserts SERR_L on the primary Reset to 0 FORWARD BRIDGE - This bit is set when poisoned TLP is detected on the primary REVERSE BRIDGE - This bit is set when address or data parity error is detected on the primary Reset to 0
26:25
DEVSEL_L Timing (medium decode)
RO
27
Signaled Target Abort
RWC
28
Received Target Abort
RWC
29
Received Master Abort
RWC
30
Signaled System Error
RWC
31
Detected Parity Error
RWC
7.5.4
REVISION ID REGISTER - OFFSET 08h
Bit
7:0
Function
Revision
Type
RO
Description
Reset to 00000000
Page 82 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.5
CLASS CODE REGISTER - OFFSET 08h
Bit
15:8
Function
Programming Interface Sub-Class Code
Type
RO
Description
Subtractive decoding of non-transparent PCI bridge not supported Reset to 00000000 Sub-Class Code 10000000: Other bridge Reset to 10000000 Base class code 00000110: Bridge Device Reset to 00000110
23:16
RO
31:24
Base Class Code
RO
7.5.6
PRIMARY CACHE LINE SIZE REGISTER - OFFSET 0Ch
Bit
1:0
Function
Reserved
Type
RO
Description
00: Cache line size of 1 DW and 2 DW are not supported Reset to 00 1: Cache line size = 4 double words Reset to 0 1: Cache line size = 8 double words Reset to 0 1: Cache line size = 16 double words Reset to 0 1: Cache line size = 32 double words Bit [7:6] not supported Reset to 00
2
Cache Line Size
RW
3
Cache Line Size
RW
4
Cache Line Size
RW
5 7:6
Cache Line Size Reserved
RW RO
7.5.7
PRIMARY LATENCY TIMER REGISTER - OFFSET 0Ch
Bit
15:8
Function
Primary Latency Timer
Type
RO / RW
Description
8 bits of primary latency timer in PCI/PCI-X FORWARD BRIDGE - RO with reset to 00h REVERSE BRIDGE - RW with reset to 00h in PCI mode or 40h in PCI-X mode
7.5.8
PRIMARY HEADER TYPE REGISTER - OFFSET 0Ch
Bit
22:16
Function
Other Bridge Configuration Single Function Device
Type
RO
Description
Type-0 header format configuration (10 - 3Fh) Reset to 0000000 0: Indicates single function device Reset to 0
23
RO
Page 83 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
31:24
Function
Reserved
Type
RO
Description
Reset to 00h
7.5.9
PRIMARY CSR AND MEMORY 0 BASE ADDRESS REGISTER - OFFSET 10h
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Downstream Memory 0 Setup Register (Offset 9Ch), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. The range of this register is from 4KB to 2GB. The lower 4KB if this address reange map to the PI7C9X130 CSRs into memory space. The remaining space is this range above 4KB, if any, specifies a range for forwarding downstream memory transactions. PI7X9X110A uses downstream Memory 0 Translated Base Register (Offset 98h) to formulate direct address translation. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
2:1
Address Type
RO
3
Prefetchable control
RO
11:4 31:12
Reserved Base Address
RO RW/RO
7.5.10
PRIMARY CSR IO BASE ADDRESS REGISTER - OFFSET 14h
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 1 Reset to 0 This Base Address Register maps to PI7C9X130 primary IO space. The maximum size is 256 bytes. Reset to 00000000h
7:1 31:8
Reserved Base Address
RO RO/RW
7.5.11
DOWNSTREAM IO OR MEMORY 1 BASE ADDRESS REGISTER - OFFSET 18h
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00
2:1
Address Type
RO
Page 84 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Bit
3
Function
Prefetchable control
Type
RO
Description
0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Downstream IO or Memory 1 Setup Register (Offset ACh), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup register to disable this register. The range of this register is from 4KB to 2GB for memory space or from 64B to 256B for IO space. PI7X9X110A uses downstream IO or Memory 1 Translated Base Register (Offset A8h) to formulate direct address translation. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
11:4 31:12
Reserved Base Address
RO RW/RO
7.5.12
DOWNSTREAM MEMORY 2 BASE ADDRESS REGISTER - OFFSET 1Ch
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01, 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Downstream Memory 2 Setup Register (CSR Offset 00Ch), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup register to disable this register. The range of this register is from 4KB to 2GB for memory space. PI7X9X110A uses downstream Memory 2 Translated Base Register (CSR Offset 008h) to formulate direct address translation. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
2:1
Address Type
RO
3
Prefetchable control
RO
11:4 31:12
Reserved Base Address
RO RW/RO
7.5.13
DOWNSTREAM MEMORY 3 BASE ADDRESS REGISTER - OFFSET 20h
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0
2:1
Address Type
RO
3
Prefetchable control
RO
11:4
Reserved
RO
Page 85 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
31:12
Function
Base Address
Type
RW/RO
Description
The size and type of this Base Address Register are defined from Downstream Memory 3 Setup Register (CSR Offset 014h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 014h and 018h) to disable this register. The range of this register is from 4KB to 9EB for memory space. PI7C9X130 uses Memory 3 Translated Base Register (CSR Offset 010h) to formulate direct address translation when 32-bit addressing programmed. When 64-bit addressing programmed, no address translation is performed. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
7.5.14
DOWNSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER - OFFSET 24h
Bit
31:0
Function
Base address
Type
RO/RW
Description
The size of this Base Address Register is defined from Downstream Memory 3 Upper 32-bit Setup Register (CSR Offset 018h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 018h) to disable this register. This register defines the upper 32 bits of a memory range for downstream forwarding memory. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000000h
7.5.15 7.5.16
RESERVED REGISTER - OFFSET 28h SUBSYSTEM ID AND SUBSYSTEM VENDOR ID REGISTER - OFFSET 2Ch
Bit
15:0
Function
Subsystem Vendor ID Subsystem ID
Type
RO
Description
Identify the vendor ID for add-in card or subsystem Reset to 0000h Identify the vendor specific device ID for add-in card or subsystem Reset to 0000h
31:16
RO
7.5.17 7.5.18
RESERVED REGISTER - OFFSET 30h CAPABILITY POINTER - OFFSET 34h
Bit
7:0
Function
Capability Pointer
Type
RO
Description
Capability pointer to 80h Reset to 80h Reset to 0
31:8
Reserved
RO
Page 86 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.19
EXPANSION ROM BASE ADDRESS REGISTER - OFFSET 38h
Bit
31:0
Function
Expansion ROM Base Address
Type
RO
Description
Expansion ROM not supported. Reset to 00000000h
7.5.20
PRIMARY INTERRUPT LINE REGISTER - OFFSET 3Ch
Bit
7:0
Function
Primary Interrupt Line
Type
RW
Description
These bits apply to reverse bridge only. For initialization code to program to tell which input of the interrupt controller the bridge's INTA_L in connected to. Reset to 00000000
7.5.21
PRIMARY INTERRUPT PIN REGISTER - OFFSET 3Ch
Bit
15:8
Function
Primary Interrupt Pin
Type
RO
Description
These bits apply to reverse bridge only. 00000001: Designates interrupt pin INTA_L is used Reset to 00h when forward mode or 01h when reverse mode.
7.5.22
PRIMARY MINIMUM GRANT REGISTER - OFFSET 3Ch
Bit
23:16
Function
Primary Minimum Grant
Type
RO
Description
This register is valid only in reverse bridge mode. It specifies how long of a burst period that PI7C9X130 needs on the primary bus in the units of 1/4 microseconds. Reset to 0
7.5.23
PRIMARY MAXIMUM LATNECY TIMER - OFFSET 3Ch
Bit
31:24
Function
Primary Maximum Latency Timer
Type
RO
Description
This register is valid only in reverse bridge mode. It specifies how often that PI7C9X130 needs to gain access to the primary bus in units of 1/4 microseconds. Reset to 0
Page 87 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.24
PCI DATA BUFFERING CONTROL REGISTER - OFFSET 40h
Bit
0
Function
Secondary Internal Arbiter's PARK Function Memory Read Prefetching Dynamic Control Disable Completion Data Prediction Control
Type
RW
Description
0: Park to the last master 1: Park to PI7C9X130 secondary port Reset to 0 0: Enable memory read prefetching dynamic control for PCI to PCIe read 1: Disable memory read prefetching dynamic control for PCI to PCIe read Reset to 0 0: Enable completion data prediction for PCI to PCIe read. 1: Disable completion data prediction Reset to 0 Reset to 0 These two bits are ignored in PCI-X mode 00: One cache line prefetch if memory read multiple address is in prefetchable range at the PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface, and the PI7C9X130 will keep remaining data after it disconnects the external master during burst read with read multiple command until the discard timer expires 10: Full prefetch if address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X130 will keep remaining data after the read multiple is terminated either by an external master or by the PI7C9X130, until the discard time expires Reset to 10 These two bits are ignored in PCI-X mode 00: Once cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X130 will keep remaining data after it is disconnected by an external master during burst read with read line command, until discard timer expires 10: Full prefetch if memory read line address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X130 will keep remaining data after the read line is terminated either by an external master or by the PI7C9X130, until the discard timer expires Reset to 00 00: One cache line prefetch if memory read address is in prefetchable range at PCI interface 01: Reserved 10: Full prefetch if memory read address is in prefetchable range at PCI interface 11: Disconnect on the first DWORD Reset to 00 0: Retry any master at PCI bus that repeats its transaction with command code changes. 1: Allows any master at PCI bus to change memory command code (MR, MRL, MRM) after it has received a retry. The PI7C9X130 will complete the memory read transaction and return data back to the master if the address and byte enables are the same. Reset to 0 Reset to 0
1
RW
2
RW
3 5:4
Reserved PCI Read Multiple Prefetch Mode
RO RW
7:6
PCI Read Line Prefetch Mode
RW
9:8
PCI Read Prefetch Mode
RW
10
PCI Special Delayed Read Mode Enable
RW
11
Reserved
RO
Page 88 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
14:12
Function
Maximum Memory Read Byte Count
Type
RW
Description
Maximum byte count is used by the PI7C9X130 when generating memory read requests on the PCIe link in response to a memory read initiated on the PCI bus and bit [9:8], bit [7:6], and bit [5:4] are set to "full prefetch". 000: 001: 010: 011: 100: 101: 110: 111: 512 bytes 128 bytes 256 bytes 512 bytes 1024 bytes 2048 bytes 4096 bytes 512 bytes
Reset to 000
7.5.25
CHIP CONTROL 0 REGISTER - OFFSET 40h
Bit
15
Function
Flow Control Update Control
Type
RW
Description
0: Flow control is updated for every two credits available 1: Flow control is updated for every on credit available Reset to 0 0: The PCI retry counter has not expired since the last reset 1: The PCI retry counter has expired since the last reset Reset to 0 00: No expiration limit 01: Allow 256 retries before expiration 10: Allow 64K retries before expiration 11: Allow 2G retries before expiration Reset to 00 0: Enable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge control register) 1: Disable the PCI discard timer in conjunction with bit [27] offset 3Ch (bridge control register) Reset to 0 0: Use bit [24] offset 3Ch for forward bridge or bit [25] offset 3Ch for reverse bridge to indicate how many PCI clocks should be allowed before the PCI discard timer expires 1: 64 PCI clocks allowed before the PCI discard timer expires Reset to 0 00: Timer expires at 25us 01: Timer expires at 0.5ms 10: Timer expires at 5ms 11: Timer expires at 25ms Reset to 01 0: Enable out-of-order capability between delayed transactions 1: Disable out-of-order capability between delayed transactions Reset to 0 00: Timer expires at 50us 01: Timer expires at 1ms 10: Timer expires at 10ms 11: Timer expires at 50ms Reset to 01
16
PCI Retry Counter Status
RWC
18:17
PCI Retry Counter Control
RW
19
PCI Discard Timer Disable
RW
20
PCI Discard Timer Short Duration
RW
22:21
Configuration Request Retry Timer Counter Value Control
RW
23
Delayed Transaction Order Control
RW
25:24
Completion Timer Counter Value Control
RW
Page 89 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
26
Function
Isochronous Traffic Support Enable
Type
RW
Description
0: All memory transactions from PCI-X to PCIe will be mapped to TC0 1: All memory transactions from PCI-X to PCIe will be mapped to Traffic Class defined in bit [29:27] of offset 40h. Reset to 0 This register can be programmed for virtual isochronous traffic mapping. By default, PI7C9X130 maps to traffic class 1. Reset to 001 0: Normal mode 1: Enable serial link interface loopback mode (TX to RX) if TM0=LOW, TM1=HIGH, TM2=HIGH, MSK_IN=HIGH, REVRSB=HIGH. PCI transaction from PCI bus will loop back to PCI bus RO for forward bridge Reset to 0 0: PI7C9X130 configuration space can be accessed from both interfaces 1: PI7C9X130 configuration space can only be accessed from the secondary interface. Primary bus accessed receives completion with CRS status for forward bridge, or target retry for reverse bridge Reset to 1 if TM0 is HIGH (the local host on secondary bus needs to program this bit to 0 after the secondary configuration programming is completed in non-transparent mode, otherwise there will be no configuration access from primary interface)
29:27
Traffic Class Used For Isochronous Traffic Serial Link Interface Loopback Enable
RW
30
RW / RO
31
Primary Configuration Access Lockout
RO / RW
7.5.26
SECONDARY COMMAND REGISTER - OFFSET 44h
Bit
0
Function
I/O Space Enable
Type
RW
Description
0: Ignore I/O transactions on the secondary interface 1: Enable response to memory transactions on the secondary interface Reset to 0 0: Ignore memory read transactions on the secondary interface 1: Enable memory read transactions on the secondary interface Reset to 0 0: Do not initiate memory or I/O transactions on the secondary interface and disable response to memory and I/O transactions on the secondary interface 1: Enable the PI7C9X130 to operate as a master on the secondary interfaces for memory and I/O transactions forwarded from the secondary interface. If the secondary of the reverse bridge is PCI-X mode, the PI7C9X130 is allowed to initiate a split completion transaction regardless of the status bit. Reset to 0 0: Bridge does not respond as a target to Special Cycle transactions, so this bit is defined as Read-Only and must return 0 when read Reset to 0 0: PI7C9X130 does not originate a Memory Write and Invalidate transaction. Implements this bit as Read-Only and returns 0 when read (unless forwarding a transaction for another master). This bit will be ignored in PCI-X mode. Reset to 0 0: Ignore VGA palette snoop access on the secondary Reset to 0
1
Memory Space Enable
RW
2
Bus Master Enable
RW
3
Special Cycle Enable
RO
4
Memory Write and Invalidate Enable
RO
5
VGA Palette Snoop Enable
RO
Page 90 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
6
Function
Parity Error Response Enable
Type
RW
Description
0: May ignore any parity error that is detected and take its normal action 1: This bit if set, enables the setting of Master Data Parity Error bit in the Status Register when poisoned TLP received or parity error is detected and takes its normal action Reset to 0 Wait cycle control not supported Reset to 0 0: Disable 1: Enable PI7C9X130 in forward bridge mode to report non-fatal or fatal error message to the Root Complex. Also, in reverse bridge mode to assert SERR_L on the secondary interface Reset to 0 Fast back-to-back enable not supported Reset to 0 0: INTx interrupt messages can be generated 1: Prevent INTx messages to be generated and any asserted INTx interrupts will be released. Reset to 0 Reset to 00000
7
Wait Cycle Control
RO
8
Secondary SERR_L Enable Bit
RW
9
Fast Back-to-Back Enable Secondary Interrupt Disable
RO
10
RO / RW
15:11
Reserved
RO
7.5.27
SECONDARY STATUS REGISTER - OFFSET 44h
Bit
18:16 19
Function
Reserved Secondary Interrupt Status
Type
RO RO
Description
Reset to 000 0: No INTx interrupt message request pending in PI7C9X130 secondary 1: INTx interrupt message request pending in PI7C9X130 secondary Reset to 0 1: PI7C9X130 supports the capability list (offset 34h in the pointer to the data structure) Reset to 1 This bit applies to forward bridge only. 1: 66MHz capable Reset to 0 when reverse bridge or 1 when forward bridge. Reset to 0 This bit applies to forward bridge only. 1: Enable fast back-to-back transactions Reset to 0 when reverse bridge or 1 when forward bridge with secondary bus in PCI mode Bit set if its Parity Error Enable bit is set and either of the conditions occurs on the secondary: REVERSE BRIDGE - * Receives a completion marked poisoned * Poisons a write request FORWARD BRIDGE - * Detected parity error when receiving data or Split Response for read * Observes P_PERR_L asserted when sending data or receiving Split Response for write * Receives a Split Completion Message indicating data parity error occurred for non-posted write Reset to 0
20
Capability List Capable
RO
21
66MHz Capable
RO
22 23
Reserved Fast Back-to-Back Capable
RO RO
24
Master Data Parity Error Detected
RWC
Page 91 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
26:25
Function
DEVSEL_L Timing (medium decode)
Type
RO
Description
These bits apply to forward bridge only. 00: 01: 10: 11: fast DEVSEL_L decoding medium DEVSEL_L decoding slow DEVSEL_L decoding reserved
27
Signaled Target Abort
RWC
Reset to 00 when reverse bridge or 01 when forward bridge. REVERSE BRIDGE - This bit is set when PI7C9X130 completes a request using completer abort status on the secondary FORWARD BRIDGE - This bit is set to indicate a target abort on the secondary Reset to 0 REVERSE BRIDGE - This bit is set when bridge receives a completion with completer abort completion status on the secondary FORWARD BRIDGE - This bit is set when PI7C9X130 detects a target abort on the secondary Reset to 0 REVERSE BRIDGE - This bit is set when PI7C9X130 receives a completion with unsupported request completion status on the secondary FORWARD BRIDGE - This bit is set when PI7C9X130 detects a master abort on the secondary REVERSE BRIDGE - This bit is set when PI7C9X130 sends an ERR_FATAL or ERR_NON_FATAL message on the secondary FORWARD BRIDGE - This bit is set when PI7C9X130 asserts SERR_L on the secondary Reset to 0 REVERSE BRIDGE - This bit is set when poisoned TLP is detected on the secondary FORWARD BRIDGE - This bit is set when address or data parity error is detected on the secondary Reset to 0
28
Received Target Abort
RWC
29
Received Master Abort
RWC
30
Signaled System Error
RWC
31
Detected Parity Error
RWC
7.5.28
ARBITER ENABLE REGISTER - OFFSET 48h
Bit
0
Function
Enable Arbiter 0
Type
RW
Description
0: Disable arbitration for internal PI7C9X130 request 1: Enable arbitration for internal PI7C9X130 request Reset to 1 0: Disable arbitration for master 1 1: Enable arbitration for master 1 Reset to 1 0: Disable arbitration for master 2 1: Enable arbitration for master 2 Reset to 1 0: Disable arbitration for master 3 1: Enable arbitration for master 3 Reset to 1
1
Enable Arbiter 1
RW
2
Enable Arbiter 2
RW
3
Enable Arbiter 3
RW
Page 92 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
4
Function
Enable Arbiter 4
Type
RW
Description
0: Disable arbitration for master 4 1: Enable arbitration for master 4 Reset to 1 0: Disable arbitration for master 5 1: Enable arbitration for master 5 Reset to 1 0: Disable arbitration for master 6 1: Enable arbitration for master 6 Reset to 1 0: Disable arbitration for master 7 1: Enable arbitration for master 7 Reset to 1 0: Disable arbitration for master 8 1: Enable arbitration for master 8 Reset to 1
5
Enable Arbiter 5
RW
6
Enable Arbiter 6
RW
7
Enable Arbiter 7
RW
8
Enable Arbiter 8
RW
7.5.29
ARBITER MODE REGISTER - OFFSET 48h
Bit
9
Function
External Arbiter Bit
Type
RO
Description
0: Enable internal arbiter (if CFN_L is tied LOW) 1: Use external arbiter (if CFN_L is tied HIGH) Reset to 0/1 according to what CFN_L is tied to 0: Broken master timeout disable 1: This bit enables the internal arbiter to count 16 PCI bus cycles while waiting for FRAME_L to become active when a device's PCI bus GNT_L is active and the PCI bus is idle. If the broken master timeout expires, the PCI bus GNT for the device is de-asserted. Reset to 0 0: A broken master will be ignored forever after de-asserting its REQ_L for at least 1 clock 1: Refresh broken master state after all the other masters have been served once Reset to 0 08h: These bits are the initialization value of a counter used by the internal arbiter. It controls the number of PCI bus cycles that the arbiter holds a device's PCI bus GNT active after detecting a PCI bus REQ_L from another device. The counter is reloaded whenever a new PCI bus GNT is asserted. For every new PCI bus GNT, the counter is armed to decrement when it detects the new fall of FRAME_L. If the arbiter fairness counter is set to 00h, the arbiter will not remove a device's PCI bus GNT until the device has de-asserted its PCI bus REQ. Reset to 08h 0: GNT_L not de-asserted after granted master assert FRAME_L 1: GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting FRAME_L Reset to 0 Reset to 0
10
Broken Master Timeout Enable
RW
11
Broken Master Refresh Enable
RW
19:12
Arbiter Fairness Counter
RW
20
GNT_L Output Toggling Enable
RW
21
Reserved
RO
Page 93 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.30
ARBITER PRIORITY REGISTER - OFFSET 48h
Bit
22
Function
Arbiter Priority 0
Type
RW
Description
0: Low priority request to internal bridge 1: High priority request to internal bridge Reset to 1 0: Low priority request to master 1 1: High priority request to master 1 Reset to 0 0: Low priority request to master 2 1: High priority request to master 2 Reset to 0 0: Low priority request to master 3 1: High priority request to master 3 Reset to 0 0: Low priority request to master 4 1: High priority request to master 4 Reset to 0 0: Low priority request to master 5 1: High priority request to master 5 Reset to 0 0: Low priority request to master 6 1: High priority request to master 6 Reset to 0 0: Low priority request to master 7 1: High priority request to master 7 Reset to 0 0: Low priority request to master 8 1: High priority request to master 8 Reset to 0 Reset to 0
23
Arbiter Priority 1
RW
24
Arbiter Priority 2
RW
25
Arbiter Priority 3
RW
26
Arbiter Priority 4
RW
27
Arbiter Priority 5
RW
28
Arbiter Priority 6
RW
29
Arbiter Priority 7
RW
30
Arbiter Priority 8
RW
31
Reserved
RO
7.5.31
SECONDARY CACHE LINE SIZE REGISTER - OFFSET 4Ch
Bit
1:0
Function
Reserved
Type
RO
Description
00: Cache line size of 1 DW and 2 DW are not supported Reset to 00 1: Cache line size = 4 double words Reset to 0 1: Cache line size = 8 double words Reset to 0 1: Cache line size = 16 double words Reset to 0 1: Cache line size = 32 double words Reset to 0
2
Cache Line Size
RW
3
Cache Line Size
RW
4
Cache Line Size
RW
5
Cache Line Size
RW
Page 94 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
7:6
Function
Reserved
Type
RO
Description
Bit [7:6] not supported Reset to 00
7.5.32
SECONDARY LATENCY TIMER REGISTER - OFFSET 4Ch
Bit
15:8
Function
Secondary Latency Timer
Type
RO / RW
Description
8 bits of secondary latency timer in PCI/PCI-X REVERSE BRIDGE - RO with reset to 00h FORWARD BRIDGE - RW with reset to 00h in PCI mode or 40h in PCI-X mode
7.5.33
SECONDARY HEADER TYPE REGISTER - OFFSET 4C
Bit
22:16
Function
Other Bridge Configuration Single Function Device Reserved
Type
RO
Description
Type-0 header format configuration (10 - 3Fh) Reset to 0000000 0: Indicates single function device Reset to 0 Reset to 00h
23
RO
31:24
RO
7.5.34
SECONDARY CSR AND MEMORY 0 BASE ADDRESS REGISTER - OFFSET 50h
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Upstream Memory 0 Setup Register (Offset E4h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. The range of this register is from 4KB to 2GB. The lower 4KB if this address reange map to the PI7C9X130 CSRs into memory space. The remaining space is this range above 4KB, if any, specifies a range for forwarding upstream memory transactions. PI7X9X110A uses upstream Memory 0 Translated Base Register (Offset E0h) to formulate direct address translation. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
2:1
Address Type
RO
3
Prefetchable control
RO
11:4 31:12
Reserved Base Address
RO RW/RO
Page 95 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.35
SECONDARY CSR IO BASE ADDRESS REGISTER - OFFSET 54h
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 1 Reset to 0 This Base Address Register maps to PI7C9X130 secondary IO space. The maximum size is 256 bytes. Reset to 00000000h
7:1 31:8
Reserved Base Address
RO RO/RW
7.5.36
UPSTREAM IO OR MEMORY 1 BASE ADDRESS REGISTER - OFFSET 58h
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Upstream IO or Memory 1 Setup Register (Offset ECh), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup register to disable this register. The range of this register is from 4KB to 2GB for memory space or from 64B to 256B for IO space. PI7X9X110A uses upstream IO or Memory 1 Translated Base Register (Offset E8h) to formulate direct address translation. If a bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW. Reset to 00000h
2:1
Address Type
RO
3
Prefetchable control
RO
5:4 31:6
Reserved Base Address
RO RW/RO
7.5.37
UPSTREAM MEMORY 2 BASE ADDRESS REGISTER - OFFSET 5Ch
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01, 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0
2:1
Address Type
RO
3
Prefetchable control
RO
13:4
Reserved
RO
Page 96 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
31:14
Function
Base Address
Type
RW/RO
Description
This Base Address register defines the address range for upstream memory transactions. PI7C9X130 uses a lookup table to do the address translation. The address range of this register is from 16KB to 2GB in memory space. The address range is divided into 64 pages. The size of each page is defined by Memory Address Forwarding Control register (Offset 6Ah), which is initialized by EEPROM (I2C) or SM Bus or local processor. Writing a zero to the bit [0] of the look up table entry can disable the corresponding page of this register (CSR Offset 1FFh: 100h). The number of writeable bit may change depending on the page size setup. Reset to 00000h
7.5.38
UPSTREAM MEMORY 3 BASE ADDRESS REGISTER - OFFSET 60h
Bit
0
Function
Space Indicator
Type
RO
Description
0: Memory space 1: IO space Reset to 0 00: 32-bit address decode range 01: 64-bit address decode range 10 and 11: reserved Reset to 00 0: Memory space is non-prefetchable 1: Memory space is prefetchable Reset to 0 Reset to 0 The size and type of this Base Address Register are defined from Upstream Memory 3 Setup Register (CSR Offset 034h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 034h and 038h) to disable this register. The range of this register is from 4KB to 9EB for memory space. PI7C9X130 uses this register and the Upstream Memory 3 Upper Base Address Register when 64-bit addressing programmed (bit [21] of Offset 68h). When 64-bit addressing is disabled, no address translation is performed. All 64-bit address transactions on the secondary interface falling outside of the Downstream Memory 3 address range are forwarded upstream. Reset to 00000h
2:1
Address Type
RO
3
Prefetchable control
RO
11:4 31:12
Reserved Base Address
RO RW/RO
7.5.39
UPSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER - OFFSET 64h
Bit
31:0
Function
Base address
Type
RO/RW
Description
The size of this Base Address Register is defined from Upstream Memory 3 Upper 32-bit Setup Register (CSR Offset 038h), which can be initialized by EEPROM (I2C) or SM Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 038h) to disable this register. This register defines the upper 32 bits of a memory range for upstream forwarding memory. PI7C9X130 uses this register and the Upstream Memory 3 Base Address Register when 64-bit addressing programmed (bit [21] of Offset 68h). When 64-bit addressing is disabled, no address translation is performed. All 64-bit address transactions on the secondary interface falling outside of the Downstream Memory 3 address range are forwarded upstream. Reset to 00000000h
Page 97 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.40
EXPRESS TRANSMITTER/RECEIVER CONTROL REGISTER - OFFSET 68h
Bit
1:0
Function
Nominal Driver Current Control
Type
RW
Description
00: 20mA 01: 10mA 10: 28mA 11: Reserved Reset to 00 0000: 1.00 x nominal driver current 0001: 1.05 x nominal driver current 0010: 1.10 x nominal driver current 0011: 1.15 x nominal driver current 0100: 1.20 x nominal driver current 0101: 1.25 x nominal driver current 0110: 1.30 x nominal driver current 0111: 1.35 x nominal driver current 1000: 1.60 x nominal driver current 1001: 1.65 x nominal driver current 1010: 1.70 x nominal driver current 1011: 1.75 x nominal driver current 1100: 1.80 x nominal driver current 1101: 1.85 x nominal driver current 1110: 1.90 x nominal driver current 1111: 1.95 x nominal driver current Reset to 0000 0000: 0.00 db 0001: -0.35 db 0010: -0.72 db 0011: -1.11 db 0100: -1.51 db 0101: -1.94 db 0110: -2.38 db 0111: -2.85 db 1000: -3.35 db 1001: -3.88 db 1010: -4.44 db 1011: -5.04 db 1100: -5.68 db 1101: -6.38 db 1110: -7.13 db 1111: -7.96 db Reset to 1000 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset to 00 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset to 00
5:2
Driver Current Scale Multiple Control
RW
11:8
Driver De-emphasis Level Control
RW
13:12
Transmitter Termination Control
RW
15:14
Receiver Termination Control
RW
Page 98 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.41
MEMORY ADDRESS FORWARDING CONTROL REGISTER - OFFSET 68h
Bit
19:16
Function
Lookup Table Page Size
Type
RW
Description
If bit [20] of Offset 68h is low, then 0000: Disable Upstream Memory 2 Base Address Register 0001: 256 bytes 0010: 512 bytes 0011: 1K bytes 0100: 2K bytes 0101: 4K bytes 0110: 8K bytes 0111: 16K bytes 1000: 32K bytes 1001: 64K bytes 1010: 128K bytes 1011: 256K bytes 1100: 512K bytes 1101: 1M bytes 1110: 2M bytes 1111: 4M bytes If bit [20] of Offset 68h is high, then 0000: Disable Upstream Memory 2 Base Address Register 0001: 8M bytes 0010: 16M bytes 0011: 32M bytes 01XX: Disable Upstream Memory 2 Base Address Register 1XXX: Disable Upstream Memory 2 Base Address Register Reset to 0h 0: Normal Lookup Table Page Size 1: Coarse Lookup Table Page Size Reset to 0 0: Any 64-bit address transactions on secondary interface falling outside of Downstream Memory 3 address range are forwarded upstream 1: Enable 64-bit address transaction forwarding upstream based on Upstream Memory 3 address range without address translation Reset to 0 Reset to 0
20
Lookup Table Page Size Extension
RW
21
Upstream 64-bit Address Range Enable
RW
29:22
Reserved
RO
7.5.42
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER - OFFSET 68h
Bit
31:30
Function
Memory Write Fragment Control
Type
RW
Description
Upstream Memory Write Fragment Control 00: Fragment at 32-byte boundary 01: Fragment at 64-byte boundary 1x: Fragement at 128-byte boundary Reset to 00h
Page 99 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.43
SUBSYSTEM VENDOR ID REGISTER - OFFSET 6Ch
Bit
15:0
Function
Subsystem Vendor ID
Type
RO
Description
Subsystem vendor ID identifies the particular add-in card or subsystem Reset to 00h
7.5.44
SUBSYSTEM ID REGISTER - OFFSET 6Ch
Bit
31:16
Function
Subsystem ID
Type
RO
Description
Subsystem ID identifies the particular add-in card or subsystem Reset to 00h
7.5.45
EEPROM AUTOLOAD CONTROL/STATUS REGISTER - OFFSET 70h
Bit
0
Function
Initiate EEPROM Read or Write Cycle
Type
RW
Description
This bit will be reset to 0 after the EEPROM operation is finished 0:EEPROM AUTOLOAD disabled 0 -> 1: Starts the EEPROM Read or Write cycle Reset to 0 0: Read 1: Write Reset to 0 0: EEPROM acknowledge is always received during the EEPROM cycle 1: EEPROM acknowledge is not received during EEPROM cycle Reset to 0 0: EEPROM autoload is not successfully completed 1: EEPROM autoload is successfully completed Reset to 0 Where PCLK is 125MHz 00: PCLK / 4096 01: PCLK / 2048 10: PCLK / 1024 11: PCLK / 128 Reset to 00 0: Enable EEPROM autoload 1: Disable EEPROM autoload Reset to 0 0: Normal speed of EEPROM autoload 1: Increase EEPROM autoload by 32x Reset to 0 0: EEPROM autoload is not on going 1: EEPROM autoload is on going Reset to 0 EEPROM word address for EEPROM cycle Reset to 0000000
1
Control Command for EEPROM
RW
2
EEPROM Error
RO
3
EPROM Autoload Complete Status
RO
5:4
EEPROM Clock Frequency Control
RW
6
EEPROM Autoload Control
RW
7
Fast EEPROM Autoload Control
RW
8
EEPROM Autoload Status
RO
15:9
EEPROM Word Address
RW
Page 100 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
31:16
Function
EEPROM Data
Type
RW
Description
EEPROM data to be written into the EEPROM Reset to 0000h
7.5.46
HOT SWAP CONTROL AND STATUS REGISTER - OFFSET 74h
Bit
7:0 15:8 16 17 18
Function
Capability ID for Hot Swap Next Capability Pointer Device Hiding Arm ENUM_L signal Mask Pending Insertion or Extraction
Type
RO RO RW RW RW
Description
Reset to 06h when Hot Sawp is enable (HS_EN=1) or 00h when Hot Swap is disabled (HS_EN=0) Reset to 00h to inidicate the end of the capability chain Device Hiding Armed when this bit is set to 1 Reset to 0 ENUM_L signal is masked when this bit is set to 1 Reset to 0 When this bit is 1, INS is armed, or either INS or EXT has a value of logic 1 When this bit is 0, INS is not armed or both INS and EXT have a value of logic 0 Reset to 0h When this bit is 1, LED is on When this bit is 0, LED is off Reset to 0 PI=01 supports PI=00 plus device hiding and pending insertion or extraction bits Reset to 01 EXT bit indicates ENUM_L status of extraction. When EXT is 1, ENUM_L is asserted Reset to 0 INS bit indicates ENUM_L status of insertion. When INS is 1, ENUM_L is asserted Reset to 1 Reset to 00h
19
LED On Off
RW
21:20
Programming Interface
RO
22
EXT for Extraction
RWC
23
INS for Insertion
RWC
31:24
Reserved
RO
7.5.47
BRIDGE CONTROL AND STATUS REGISTER - OFFSET 78h
Bit
1:0 2
Function
Reserved SERR_L Forward Enable
Type
RO RW/RO
Description
Reset to 00 0: Disable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL 1: Enable the forwarding of SERR_L to ERR_FATAL and ERR_NONFATAL Reset to 0 (FORWARD BRIDGE) RO bit for REVERSE BRIDGE 0: Do not force the assertion of RESET_L on secondary PCI/PCI-X bus in forward bridge mode, or do not generate a hot reset on the PCI Express link in reverse bridge mode 1: Force the assertion of RESET_L on secondary PCI/PCI-X bus in forward bridge mode, or generate a hot reset on the PCI Express link in reverse bridge mode Reset to 0
3
Secondary Interface Reset
RW
Page 101 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
5:4
Function
VGA Enable
Type
RW
Description
00: VGA memory and I/O transactions on the primary and secondary interfaces are ignored, unless decoded by other mechanism 01: VGA memory and I/O transactions on the primary interface are forwarded to secondary interface without address translation, but VGA transactions on secondary interface are ignored 10: VGA memory and I/O transactions on the secondary interface are forwarded to primary interface without address translation, but VGA transactions on primary interface are ignored Reset to 00 0: Execute 10-bit address decodes on VGA I/O accesses 1: Execute 16-bit address decode on VGA I/O accesses Reset to 0 0: Do not report master aborts (return FFFFFFFFh on reads and discards data on write) 1: Report master abort by signaling target abort if possible or by the assertion of SERR_L (if enabled). Reset to 0 0: Primary discard timer counts 215 PCI clock cycles 1: Primary discard timer counts 210 PCI clock cycles FORWARD BRIDGE - Bit is RO and ignored by PI7C9X130 Reset to 0 0: Secondary discard timer counts 215 PCI clock cycles 1: Secondary discard timer counts 210 PCI clock cycles REVERSE BRIDGE - Bit is RO and ignored by PI7C9X130 Reset to 0 Bit is set when the discard timer expires and a delayed completion is discarded at the PCI interface for the forward or reverse bridge Reset to 0 Bit is set to enable to generate ERR_NONFATAL or ERR_FATAL for forward bridge, or assert SERR_L for reverse bridge as a result of the expiration of the discard timer. It has no meaning if PI7C9X130 is in PCI-X mode. Reset to 0
6
VGA 16-bit Decode
RW
7
Master Abort Mode
RW
8
Primary Master Timeout
RW
9
Secondary Master Timeout
RW
10
Master Timeout Status
RWC
11
Discard Timer SERR_L Enable
RW
7.5.48
GPIO DATA AND CONTROL REGISTER - OFFSET 78h
Bit
15:12 19:16 23:20 27:24 31:28
Function
GPIO Output Write1-to-Clear GPIO Output Write1-to-Set GPIO Output Enable Write-1-to-Clear GPIO Output Enable Write-1-to-Set GPIO Input Data Register
Type
RW RW RW RW RO
Description
Reset to 0h Reset to 0h Reset to 0h Reset to 0h Reset to 0h
Page 102 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.49
SECONDARY INTERRUPT LINE REGISTER - OFFSET 7Ch
Bit
7:0
Function
Secondary Interrupt Line
Type
RW
Description
These bits apply to forward bridge only. For initialization code to program to tell which input of the interrupt controller the bridge's INTA_L in connected to. Reset to 00000000
7.5.50
SECONDARY INTERRUPT PIN REGISTER - OFFSET 7Ch
Bit
15:8
Function
Secondary Interrupt Pin
Type
RO
Description
These bits apply to forward bridge only. 00000001: Designates interrupt pin INTA_L is used Reset to 00h when reverse mode or 01h when forward mode.
7.5.51
SECONDARY MINIMUM GRANT REGISTER - OFFSET 7Ch
Bit
23:16
Function
Secondary Minimum Grant
Type
RO
Description
This register is valid only in forward bridge mode. It specifies how long of a burst period that PI7C9X130 needs on the secondary bus in the units of 1/4 microseconds. Reset to 0
7.5.52
SECONDARY MAXIMUM LATENCY TIMER - OFFSET 7Ch
Bit
31:24
Function
Secondary Maximum Latency Timer
Type
RO
Description
This register is valid only in forward bridge mode. It specifies how often that PI7C9X130 needs to gain access to the primary bus in units of 1/4 microseconds. Reset to 0
7.5.53
PCI-X CAPABILITY ID REGISTER - OFFSET 80h
Bit
7:0
Function
PCI-X Capability ID
Type
RO
Description
PCI-X Capability ID Reset to 07h
7.5.54
NEXT CAPABILITY POINTER REGISTER - OFFSET 80h
Bit
15:8
Function
Next Capability Pointer
Type
RO
Description
Point to power management Reset to 90h
Page 103 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.55
PCI-X SECONDARY STATUS REGISTER - OFFSET 80h
Bit
16
Function
64-bit Device on Secondary Bus Interface 133MHz Capable
Type
RO
Description
64-bit supported when DEV64 is set to high Reset to 1in forward bridge mode and DEV64 is set to high or reset to 0 in reverse bridge mode When this bit is 1, PI7C9X130 is 133MHz capable on its secondary bus interface Reset to 1 in forward bridge mode or 0 in reverse bridge mode This bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode When this is set to 1, a split completion has been discarded by PI7C9X130 at secondary bus because the requester did not accept the split completion transaction Reset to 0 This bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode When this bit is set to 1, an unexpected split completion has been received with the requester ID equaled to the secondary bus number, device number, and function number at the PI7X9X130 secondary bus interface Reset to 0 When this bit is set to 1, a split completion has been terminated by PI7C9X130 with either a retry or disconnect at the next ADB due to the buffer full condition Reset to 0 When this bit is set to 1, a split request is delayed because PI7C9X130 is not able to forward the split request transaction to its secondary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register Reset to 0 These bits are only meaningful in forward bridge mode. In reverse bridge mode, all three bits are set to zero. 000: Conventional PCI mode (minimum clock period not applicable) 001: 66MHz (minimum clock period is 15ns) 010: 100 to 133MHz (minimum clock period is 7.5ns) 011: Reserved 1xx: Reserved Reset to 000 0000000
17
RO
18
Split Completion Discarded
RO / RWC
19
Unexpected Split Completion
RWC
20
Split Completion Overrun
RWC
21
Split Request Delayed
RWC
24:22
Secondary Clock Frequency
RO
31:25
Reserved
RO
7.5.56
PCI-X BRIDGE STATUS REGISTER - OFFSET 84h
Bit
2:0
Function
Function Number
Type
RO
Description
Function number (AD [10:8] of a type 0 configuration transaction) Reset to 000
Page 104 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
7:3
Function
Device Number
Type
RO
Description
Device number (AD [15:11] of a type 0 configuration transaction) is assigned to the PI7C9X130 by the connection of system hardware. Each time the PI7C9X130 is addressed by a configuration write transaction, the bridge updates this register with the contents of AD [15:11] of the address phase of the configuration transaction, regardless of which register in the PI7C9X130 is addressed by the transaction. The PI7C9X130 is addressed by a configuration write transaction if all of the following are true: * The transaction uses a configuration write command * IDSEL is asserted during the address phase * AD [1:0] are 00 (type o configuration transaction) * AD [10:8] of the configuration address contain the appropriate function number Reset to 11111 Additional address from which the contents of the primary bus number register on type 1 configuration space header is read. The PI7C9X130 uses the bus number, device number, and function number fields to create a completer ID when responding with a split completion to a read of an internal PI7C9X130 register. These fields are also used for cases when one interface is in conventional PCI mode and the other is in PCI-X mode. Reset to 11111111 64-bit supported when DEV64 is set to high Reset to 0 in forward bridge mode or in reverse bridge mode with REQ64_L is high at the de-assertion of RESET_L or reset to 1 in reverse bridge mode with REQ64_L is low at the de-assertion of RESET_L When this bit is 1, PI7C9X130 is 133MHz capable on its primary bus interface Reset to 0 in forward bridge mode or 1 in reverse bridge mode This bit is a read-only and set to 0 in reverse bridge mode or is read-write in forward bridge mode When this is set to 1, a split completion has been discarded by PI7C9X130 at primary bus because the requester did not accept the split completion transaction Reset to 0 This bit is set to 0 in forward bridge mode or is read-write in reverse bridge mode When this is set to 1, an unexpected split completion has been received with the requester ID equaled to the primary bus number, device number, and function number at the PI7X9X130 primary bus interface Reset to 0 When this bit is set to 1, a split completion has been terminated by PI7C9X130 with either a retry or disconnect at the next ADB due to the buffer full condition Reset to 0 When this bit is set to 1, a split request is delayed because PI7C9X130 is not able to forward the split request transaction to its primary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register Reset to 0 0000000000
15:8
Bus Number
RO
16
64-bit Device on Primary Bus Interface
RO
17
133MHz Capable
RO
18
Split Completion Discarded
RO / RWC
19
Unexpected Split Completion
RWC
20
Split Completion Overrun
RWC
21
Split Request Delayed
RWC
31:22
Reserved
RO
Page 105 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.57
UPSTREAM SPLIT TRANSACTION REGISTER - OFFSET 88h
Bit
15:0
Function
Upstream Split Transaction Capability
Type
RO
Description
Upstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the secondary bus in addressing the completers on the primary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h Upstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X130 is allowed to forward all split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h
31:16
Split Transaction Commitment Limit
RW
7.5.58
DOWNSTREAM SPLIT TRANSACTION REGISTER - OFFSET 8Ch
Bit
15:0
Function
Downstream Split Transaction Capability
Type
RO
Description
Downstream Split Transaction Capability specifies the size of the buffer (in the unit of ADQs) to store split completions for memory read. It applies to the requesters on the primary bus in addressing the completers on the secondary bus. The 0010h value shows that the buffer has 16 ADQs or 2K bytes storage Reset to 0010h Downstream Split Transaction Commitment Limit indicates the cumulative sequence size of the commitment limit in units of ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X130 is allowed to forward all split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability. Reset to 0010h
31:16
Downstream Split Transaction Commitment Limit
RW
7.5.59
POWER MANAGEMENT ID REGISTER - OFFSET 90h
Bit
7:0
Function
Power Management ID
Type
RO
Description
Power management ID = 01h Reset to 01h
7.5.60
NEXT CAPABILITY POINTER REGISTER - OFFSET 90h
Bit
15:8
Function
Next Pointer
Type
RO
Description
Next pointer (point to Subsystem ID and Subsystem Vendor ID) Reset to A8h
Page 106 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.61
POWER MANAGEMENT CAPABILITY REGISTER - OFFSET 90h
Bit
18:16
Function
Version Number
Type
RO
Description
Version number that complies with revision 2.0 of the PCI Power Management Interface specification. Reset to 010 PME clock is not required for PME_L generation Reset to 0 Reset to 0 DSI - no special initialization of this function beyond the standard PCI configuration header is required following transition to the D0 un-initialized state Reset to 0 000: 0mA 001: 55mA 010: 100mA 011: 160mA 100: 220mA 101: 270mA 110: 320mA 111: 375mA Reset to 001 D1 power management is not supported Reset to 0 D2 power management is not supported Reset to 0 PME_L is supported in D3 cold, D3 hot, and D0 states. Reset to 11001
19
PME Clock
RO
20 21
Reserved Device Specific Initialization (DSI)
RO RO
24:22
AUX Current
RO
25
D1 Power Management D2 Power Management PME_L Support
RO
26
RO
31:27
RO
7.5.62
POWER MANAGEMENT CONTROL AND STATUS REGISTER - OFFSET 94h
Bit
1:0
Function
Power State
Type
RW
Description
Power State is used to determine the current power state of PI7C9X130. If a non-implemented state is written to this register, PI7C9X130 will ignore the write data. When present state is D3 and changing to D0 state by programming this register, the power state change causes a device reset without activating the RESET_L of PCI/PCI-X bus interface 00: D0 state 01: D1 state not implemented 10: D2 state not implemented 11: D3 state Reset to 00 Reset to 000000 0: PME_L assertion is disabled 1: PME_L assertion is enabled Reset to 0 Data register is not implemented Reset to 0000
7:2 8
Reserved PME Enable
RO RWS
12:9
Data Select
RO
Page 107 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
14:13
Function
Data Scale
Type
RO
Description
Data register is not implemented Reset to 00 PME_L is supported Reset to 0
15
PME Status
RWCS
7.5.63
PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER - OFFSET 94h
Bit
21:16 22
Function
Reserved B2/B3 Support
Type
RO RO
Description
Reset to 000000 B2 / B3 not support for D3hot Reset to 0 PCI Bus Power/Clock Disabled Reset to 0 Data register is not implemented Reset to 00h
23
PCI Bus Power/Clock Control Data Register
RO
31:24
RO
7.5.64
DOWNSTREAM MEMORY 0 TRANSLATED BASE REGISTER - OFFSET 98h
Bit
11:0 31:12
Function
Reserved Downstream Memory 0 Translated Base
Type
RO RW
Description
Reset to 000h Define the translated base address for downstream memory transactions whose initiator addresses fall into Downstream Memory 0 (above lower 4K boundary) address range. The number of bits that are used for translated base is determined by its setup register (offset 9Ch) Reset to 00000h
7.5.65
DOWNSTREAM MEMORY 0 SETUP REGISTER - OFFSET 9Ch
Bit
0
Function
Type Selector
Type
RO
Description
0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00h 0: Set the corresponding bit in the Base Address Register to read only. 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. Reset to 7FFFFh Always set to 1 when a bus master attempts to write a zero to this bit. PI7C9X130 returns bit [31:12] as FFFFFh (for 4KB size). Reset to 1
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
11:4 30:12
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
Page 108 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
7.5.66
CAPABILITY ID REGISTER - OFFSET A0h
Bit
7:0
Function
Capability ID
Type
RO
Description
Capability ID for SI Reset to 04h
7.5.67
NEXT POINTER REGISTER - OFFSET A0h
Bit
15:8
Function
Next Pointer
Type
RO
Description
Next pointer - points to PCI Express capabilities register Reset to B0h
7.5.68
SLOT NUMBER REGISTER - OFFSET A0h
Bit
20:16
Function
Expansion Slot Number First In Chassis
Type
RW
Description
Expansion slot number Reset to 00000 First in chassis Reset to 0 Reset to 00
21
RW
23:22
Reserved
RO
7.5.69
CHASSIS NUMBER REGISTER - OFFSET A0h
Bit
31:24
Function
Chassis Number
Type
RW
Description
Chassis number Reset to 00h
7.5.70
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER - OFFSET A4h
Bit
1:0
Function
CLKOUT0 Enable
Type
RW
Description
CLKOUT (Slot 0) Enable 00: enable CLKOUT0 01: enable CLKOUT0 10: enable CLKOUT0 11: disable CLKOUT0 and driven LOW Reset to 00 CLKOUT (Slot 1) Enable 00: enable CLKOUT1 01: enable CLKOUT1 10: enable CLKOUT1 11: disable CLKOUT1 and driven LOW Reset to 00
3:2
CLKOUT1 Enable
RW
Page 109 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
5:4
Function
CLKOUT2 Enable
Type
RW
Description
CLKOUT (Slot 2) Enable 00: enable CLKOUT2 01: enable CLKOUT2 10: enable CLKOUT2 11: disable CLKOUT2 and driven LOW Reset to 00 CLKOUT (Slot 3) Enable 00: enable CLKOUT3 01: enable CLKOUT3 10: enable CLKOUT3 11: disable CLKOUT3 and driven LOW Reset to 00 CLKOUT (Device 1) Enable 0: enable CLKOUT4 1: disable CLKOUT4 and driven LOW Reset to 0 CLKOUT (Device 2) Enable 0: enable CLKOUT5 1: disable CLKOUT5 and driven LOW Reset to 0 CLKOUT (the bridge) Enable for forward bridge mode only 0: enable CLKOUT6 1: disable CLKOUT6 and driven LOW Reset to 0 Reset to 0 Reset to 0 Secondary clock stop status 0: secondary clock not stopped 1: secondary clock stopped Reset to 0 0: disable protocol 1: enable protocol Reset to 0 0: Stop the secondary clock only when PI7C9X130 is at D3hot state 1: Stop the secondary clock whenever the secondary bus is idle and there are no requests from the primary bus Reset to 0 Reset 0000h
7:6
CLKOUT3 Enable
RW
8
CLKOUT4 Enable
RW
9
CLKOUT5 Enable
RW
10
CLKOUT6 Enable
RW
11 12 13
Reserved Reserved Secondary Clock Stop Status
RO RO RO
14
Secondary Clkrun Protocol Enable
RW
15
Clkrun Mode
RW
31:16
Reserved
RO
7.5.71
DOWNSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER - OFFSET A8h
Bit
5:0
Function
Reserved
Type
RO
Description
Reset to 000000
Page 110 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
31:6
Function
Downstream I/O or Memory 1 Translated Base
Type
RW
Description
Define the translated base address for downstream I/O or memory transactions whose initiator addresses fall into Downstream I/O or Memory 1 address range. The number of bits that are used for translated base is determined by its setup register (offset ACh) Reset to 00000h
7.5.72
DOWNSTREAM I/O OR MEMORY 1 SETUP REGISTER - OFFSET ACh
Bit
0
Function
Type Selector
Type
RO
Description
0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only. 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. If memory space is selected, bit [11:6] should be set to zeros. Reset to 00000000h 0: Disable this Base Address Register 1: Enable this Base Address Register Reset to 0
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
5:4 30:6
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
7.5.73
CAPABILITY ID REGISTER - OFFSET B0h
Bit
7:0
Function
PCI Express Capability ID
Type
RO
Description
PCI Express capability ID Reset to 10h
7.5.74
NEXT CAPABILITY POINTER REGISTER - OFFSET B0h
Bit
15:8
Function
Next Item Pointer
Type
RO
Description
Next item pointer (points to VPD register) Reset to D8h
7.5.75
PCI EXPRESS CAPABILITY REGISTER - OFFSET B0h
Bit
19:16
Function
Capability Version
Type
RO
Description
Reset to 1h
Page 111 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
23:20
Function
Device / Port Type
Type
RO
Description
0000: PCI Express endpoint device 0001: Legacy PCI Express endpoint device 0100: Root port of PCI Express root complex 0101: Upstream port of PCI Express switch 0110: Downstream port of PCI Express switch 0111: PCI Express to PCI bridge 1000: PCI to PCI Express bridge Others: Reserved Reset to 7h for Forward Bridge or 8h for Reverse Bridge Reset to 0h for Forward Bridge or 1h for Reverse Bridge Reset to 0h Reset to 0
24 29:25 31:30
Slot Implemented Interrupt Message Number Reserved
RO RO RO
7.5.76
DEVICE CAPABILITY REGISTER - OFFSET B4h
Bit
2:0
Function
Maximum Payload Size
Type
RO
Description
000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 001 No phantom functions supported Reset to 0 8-bit tag field supported Reset to 1h Endpoint L0's acceptable latency 000: less than 64 ns 001: 64 - 128 ns 010: 128 - 256 ns 011: 256 - 512 ns 100: 512 ns - 1 us 101: 1 - 2 us 110: 2 - 4 us 111: more than 4 us Reset to 000 Endpoint L1's acceptable latency 000: less than 1 us 001: 1 - 2 us 010: 2 - 4 us 011: 4 - 8 us 100: 8 - 16 us 101: 16 - 32 us 110: 32 - 64 us 111: more than 64 us Reset to 000 0: If Hot Plug is disabled 1: If Hot Plug is enabled at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping.
4:3
Phantom Functions
RO
5
8-bit Tag Field
RO
8:6
Endpoint L0's Latency
RO
11:9
Endpoint L1's Latency
RO
12
Attention Button Present
RO
Page 112 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
13
Function
Attention Indicator Present
Type
RO
Description
0: If Hot Plug is disabled 1: If Hot Plug is enable at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enable at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 000 These bits are set by the Set_Slot_Power_Limit message Reset to 00h This value is set by the Set_Slot_Power_Limit message Reset to 00 Reset to 0h
14
Power Indicator Present
RO
17:15 25:18
Reserved Captured Slot Power Limit Value Captured Slot Power Limit Scale Reserved
RO RO
27:26
RO
31:28
RO
7.5.77
DEVICE CONTROL REGISTER - OFFSET B8h
Bit
0 1 2 3
Function
Correctable Error Reporting Enable Non-Fatal Error Reporting Enable Fatal Error Reporting Enable Unsupported Request Reporting Enable Relaxed Ordering Enable Max Payload Size
Type
RW RW RW RW
Description
Reset to 0h Reset to 0h Reset to 0h Reset to 0h
4 7:5
RO RW
Reset to 0h This field sets the maximum TLP payload size for the bridge 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 000 Reset to 0 Phantom functions not supported Reset to 0 Auxiliary power PM not supported Reset to 0 PI7C9X130 never sets the No Snoop attribute in the transaction it initiates Reset to 0
8 9
Extended Tag Field Enable Phantom Functions Enable Auxiliary Power PM Enable No Snoop Enable
RW RO
10
RO
11
RO
Page 113 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
14:12
Function
Maximum Read Request Size
Type
RW
Description
This field sets the maximum Read Request Size for the device as a requester 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 2h Reset to 0
15
Configuration Retry Enable
RW
7.5.78
DEVICE STATUS REGISTER - OFFSET B8h
Bit
16 17 18 19 20 21
Function
Correctable Error Detected Non-Fatal Error Detected Fatal Error Detected Unsupported Request Detected AUX Power Detected Transaction Pending
Type
RWC RWC RWC RWC RO RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1 0: No transaction is pending on transaction layer interface 1: Transaction is pending on transaction layer interface Reset to 0 Reset to 0000000000
31:22
Reserved
RO
7.5.79
LINK CAPABILITY REGISTER - OFFSET BCh
Bit
3:0
Function
Maximum Link Speed
Type
RO
Description
Indicates the maximum speed of the Express link 0001: 2.5Gb/s link Reset to 1 Indicates the maximum width of the Express link 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 Reset to 000001
9:4
Maximum Link Width
RO
Page 114 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE
Bit
11:10
Function
ASPM Support
Type
RO
Description
This field indicates the level of Active State Power Management Support 00: reserved 01: L0's entry supported 10: reserved 11: L0's and L1's supported Reset to 0 Reset to 3h Reset to 0h Reset to 0h Reset to 00h
14:12 17:15 23:18 31:24
L0's Exit Latency L1's Exit Latency Reserved Port Number
RO RO RO RO
7.5.80
LINK CONTROL REGISTER - OFFSET C0h
Bit
1:0
Function
ASPM Control
Type
RW
Description
This field controls the level of ASPM supported on the Express link 00: disabled 01: L0's entry enabled 10: L1's entry enabled 11: L0's and L1's entry enabled Reset to 00 Reset to 0 Read completion boundary not supported Reset to 0 RO for Forward Bridge Reset to 0 RO for Forward Bridge Reset to 0 Reset to 0 Reset to 0 Reset to 00h
2 3
Reserved Read Completion Boundary (RCB) Link Disable
RO RO
4
RO / RW
5
Retrain Link
RO / RW
6 7 15:8
Common Clock Configuration Extended Sync Reserved
RW RW RO
7.5.81
LINK STATUS REGISTER - OFFSET C0h
Bit
19:16
Function
Link Speed
Type
RO
Description
This field indicates the negotiated speed of the Express link 001: 2.5Gb/s link Reset to 1h 000000: reserved 000001: x1 000010: x2 000100: x4 001000: x8 001100: x12 010000: x16 100000: x32 Reset to 000001 Reset to 0 Reset to 0
25:20
Negotiated Link Width
RO
26 27
Link Train Error Link Training
RO RO
Page 115 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Bit
28 31:29
Function
Slot Clock Configuration Reserved
Type
RO RO
Description
Reset to 1 Reset to 0
7.5.82
SLOT CAPABILITY REGISTER - OFFSET C4h
Bit
0
Function
Attention Button Present
Type
RO
Description
0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 0 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 0 0: If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. Reset to 00h Reset to 00 Reset to 00 Reset to 0
1 2
Power Controller Present MRL Sensor Present
RO RO
3
Attention Indicator Present
RO
4
Power Indicator Present
RO
5 6
Hot Plug Surprise Hot Plug Capable
RO RO
14:7 16:15 18:17 31:19
Slot Power Limit Value Slot Power Limit Scale Reserved Physical Slot Number
RO RO RO RO
7.5.83
SLOT CONTROL REGISTER - OFFSET C8h
Bit
0 1 2 3 4
Function
Attention Button Present Enable Power Fault Detected Enable MRL Sensor Changed Enable Presence Detect Changed Enable Command Completed Interrupt Enable Hot Plug Interrupt Enable
Type
RW RW RW RW RW
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
5
RW
Reset to 0
Page 116 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Bit
7:6 9:8 10 15:11
Function
Attention Indicator Control Power Indicator Control Power Controller Control Reserved
Type
RW RW RW RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.84
SLOT STATUS REGISTER - OFFSET C8h
Bit
16 17 18 19 20 21 22 31:23
Function
Attention Button Pressed Power Fault Detected MRL Sensor Changed Presence Detect Changed Command Completed MRL Sensor State Presence Detect State Reserved
Type
RO RO RO RO RO RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.85
XPIP CONFIGURATION REGISTER 0 - OFFSET CCh
Bit
0 1 2 3
Function
Hot Reset Enable Loopback Function Enable Cross Link Function Enable Software Direct to Configuration State when in LTSSM state Internal Selection for Debug Mode Negotiate Lane Number of Times TS1 Number Counter Reserved LTSSM Enter L1 Timer Default Value
Type
RW RW RW RW
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
4 7:5 12:8 15:13 31:16
RW RW RW RO RW
Reset to 0 Reset to 3h Reset to 10h Reset to 0 Reset to 0400h
7.5.86
XPIP CONFIGURATION REGISTER 1 - OFFSET D0h
Bit
9:0 15:10 31:16
Function
L0's Lifetime Timer Reserved L1 Lifetime Timer
Type
RW RO RW
Description
Reset to 0 Reset to 0 Reset to 0
Page 117 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.5.87
XPIP CONFIGURATION REGISTER 2 - OFFSET D4h
Bit
7:0 14:8 15 22:16 31:23
Function
CDR Recovery Time (in FTS units) L0's Exit to L0 Latency Reserved L1 Exit to L0 Latency Reserved
Type
RW RW RO RW RO
Description
Reset to 54h Reset to 2h Reset to 0 Reset to 19h Reset to 0
7.5.88
CAPABILITY ID REGISTER - OFFSET D8h
Bit
7:0
Function
Capability ID for VPD Register
Type
RO
Description
Reset to 03h
7.5.89
NEXT POINTER REGISTER - OFFSET D8h
Bit
15:8
Function
Next Pointer
Type
RO
Description
Next pointer (F0h, points to MSI capabilities) Reset to F0h
7.5.90
VPD REGISTER - OFFSET D8h
Bit
17:16 23:18 30:24 31
Function
Reserved VPD Address for Read/Write Cycle Reserved VPD Operation
Type
RO RW RO RW
Description
Reset to 0 Reset to 0 Reset to 0 0: Generate a read cycle from the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at `0' until EEPROM cycle is finished, after which the bit is then set to `1'. Data for reads is available at register ECh. 1: Generate a write cycle to the EEPROM at the VPD address specified in bits [7:2] of offset D8h. This bit remains at `1' until EEPROM cycle is finished, after which it is then cleared to `0'. Reset to 0
7.5.91
VPD DATA REGISTER - OFFSET DCh
Bit
31:0
Function
VPD Data
Type
RW
Description
VPD Data (EEPROM data [address + 0x40]) The least significant byte of this register corresponds to the byte of VPD at the address specified by the VPD address register. The data read form or written to this register uses the normal PCI byte transfer capabilities. Reset to 0
Page 118 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.5.92
UPSTREAM MEMORY 0 TRANSLATED BASE - OFFSET E0h
Bit
11:0 31:12
Function
Reserved Downstream Memory 0 Translated Base
Type
RO RW
Description
Reset to 000h Define the translated base address for upstream memory transactions whose initiator addresses fall into Upstream Memory 0 (above lower 4K boundary) address range. The number of bits that are used for translated base is determined by its setup register (offset E4h) Reset to 00000h
7.5.93
UPSTREAM MEMORY 0 SETUP REGISTER - OFFSET E4h
Bit
0
Function
Type Selector
Type
RO
Description
0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00h 0: Set the corresponding bit in the Base Address Register to read only. 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. Reset to 00000h Always set to 1 when a bus master attempts to write a zero to this bit. PI7C9X130 returns bit [31:12] as FFFFFh (for 4KB size). Reset to 1
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
11:4 30:12
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
7.5.94
UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER - OFFSET E8h
Bit
5:0 31:6
Function
Reserved Upstream I/O or Memory 1 Translated Base
Type
RO RW
Description
Reset to 000000 Define the translated base address for upstream I/O or memory transactions whose initiator addresses fall into Upstream I/O or Memory 1 address range. The number of bits that are used for translated base is determined by its setup register (offset ECh) Reset to 00000h
7.5.95
UPSTREAM I/O OR MEMORY 1 SETUP REGISTER - OFFSET ECh
Bit
0
Function
Type Selector
Type
RO
Description
0: Memory space is requested Reset to 0
Page 119 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Bit
2:1
Function
Address Type
Type
RO (WS)
Description
00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only. 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. If memory space is selected, bit [11:6] should be set to zeros. Reset to 00000000h 0: Disable this Base Address Register 1: Enable this Base Address Register Reset to 0
3
Prefetchable Control
RO (WS)
5:4 30:6
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
7.5.96
MESSAGE SIGNALED INTERRUPTS ID REGISTER - OFFSET F0h
Bit
7:0
Function
Capability ID for MSI Registers
Type
RO
Description
Reset to 05h
7.5.97
NEXT CAPABILITY POINTER REGISTER - OFFSET F0h
Bit
15:8
Function
Next Pointer
Type
RO
Description
Next pointer (00h indicates the end of capabilities) Reset to 00h
7.5.98
MESSAGE CONTROL REGISTER - OFFSET F0h
Bit
16
Function
MSI Enable
Type
RW
Description
0: Disable MSI and default to INTx for interrupt 1: Enable MSI for interrupt service and ignore INTx interrupt pins 000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000
19:17
Multiple Message Capable
RO
Page 120 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Bit
22:20
Function
Multiple Message Enable
Type
RW
Description
000: 1 message requested 001: 2 messages requested 010: 4 messages requested 011: 8 messages requested 100: 16 messages requested 101: 32 messages requested 110: reserved 111: reserved Reset to 000 Reset to 1 Reset to 00h
23 31:24
64-bit Address Capable Reserved
RW RO
7.5.99
MESSAGE ADDRESS REGISTER - OFFSET F4h
Bit
1:0 31:2
Function
Reserved System Specified Message Address
Type
RO RW
Description
Reset to 00 Reset to 0
7.5.100 MESSAGE UPPER ADDRESS REGISTER - OFFSET F8h
Bit
31:0
Function
System Specified Message Upper Address
Type
RW
Description
Reset to 0
7.5.101 MESSAGE DATA REGISTER - OFFSET FCh
Bit
15:0 31:16
Function
System Specified Message Data Reserved
Type
RW RO
Description
Reset to 0 Reset to 0
7.5.102 ADVANCE ERROR REPORTING CAPABILITY ID REGISTER - OFFSET 100h
Bit
15:0
Function
Advance Error Reporting Capability ID
Type
RO
Description
Reset to 0001h
7.5.103 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER - OFFSET 100h
Bit
19:16
Function
Advance Error Reporting Capability Version
Type
RO
Description
Reset to 1h
Page 121 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.5.104 NEXT CAPABILITY OFFSET REGISTER - OFFSET 100h
Bit
31:20
Function
Next Capability Offset
Type
RO
Description
Next capability offset (150h points to VC capability) Reset to 150h
7.5.105 UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 104h
Bit
0 3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21
Function
Training Error Status Reserved Data Link Protocol Error Status Reserved Poisoned TLP Status Flow Control Protocol Error Status Completion Timeout Status Completer Abort Status Unexpected Completion Status Receiver Overflow Status Malformed TLP Status ECRC Error Status Unsupported Request Error Status Reserved
Type
RWCS RO RWCS RO RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RWCS RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.106 UNCORRECTABLE ERROR MASK REGISTER - OFFSET 108h
Bit
0 3:1 4 11:5 12 13 14 15 16 17 18 19 20 31:21
Function
Training Error Mast Reserved Data Link Protocol Error Mask Reserved Poisoned TLP Mask Flow Control Protocol Error Mask Completion Timeout Mask Completion Abort Mask Unexpected Completion Mask Receiver Overflow Mask Malformed TLP Mask ECRC Error Mask Unsupported Request Error Mask Reserved
Type
RWS RO RWS RO RWS RWS RWS RWS RWS RWS RWS RWS RWS RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
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7.5.107 UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 10Ch
Bit
0 3:1 4 11:5 12 13
Function
Training Error Severity Reserved Data Link Protocol Error Severity Reserved Poisoned TLP Severity Flow Control Protocol Error Severity Completion Timeout Severity Completer Abort Severity Unexpected Completion Severity Receiver Overflow Severity Malformed TLP Severity ECRC Error Severity Unsupported Request Error Severity Reserved
Type
RWS RO RWS RO RWS RWS
Description
Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0 Reset to 1
14 15 16 17 18 19 20
RWS RWS RWS RWS RWS RWS RWS
Reset to 0 Reset to 0 Reset to 0 Reset to 1 Reset to 1 Reset to 0 Reset to 0
31:21
RO
Reset to 0
7.5.108 CORRECTABLE ERROR STATUS REGISTER - OFFSET 110h
Bit
0 5:1 6 7 8 11:9 12 31:13
Function
Receiver Error Status Reserved Bad TLP Status Bad DLLP Status REPLAY_NUM Rollover Status Reserved Replay Timer Timeout Status Reserved
Type
RWCS RO RWCS RWCS RWCS RO RWCS RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.109 CORRECTABLE ERROR MASK REGISTER - OFFSET 114h
Bit
0 5:1 6 7 8 11:9
Function
Receiver Error Mask Reserved Bad TLP Mask Bad DLLP Mask REPLAY_NUM Rollover Mask Reserved
Type
RWS RO RWS RWS RWS RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
Page 123 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Bit
12 31:13
Function
Replay Timer Timeout Mask Reserved
Type
RWS RO
Description
Reset to 0 Reset to 0
7.5.110 ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER - OFFSET 118h
Bit
4:0 5 6 7 8 31:9
Function
First Error Pointer ECRC Generation Capable ECRC Generation Enable ECRC Check Capable ECRC Check Enable Reserved
Type
ROS RO RWS RO RWS RO
Description
Reset to 0h Reset to 1 Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.5.111 HEADER LOG REGISTER 1 - OFFSET 11Ch
Bit
7:0 15:8 23:16 31:24
Function
Header Byte 3 Header Byte 2 Header Byte 1 Header Byte 0
Type
ROS ROS ROS ROS
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.112 HEADER LOG REGISTER 2 - OFFSET 120h
Bit
7:0 15:8 23:16 31:24
Function
Header Byte 7 Header Byte 6 Header Byte 5 Header Byte 4
Type
ROS ROS ROS ROS
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.113 HEADER LOG REGISTER 3 - OFFSET 124h
Bit
7:0 15:8 23:16 31:24
Function
Header Byte 11 Header Byte 10 Header Byte 9 Header Byte 8
Type
ROS ROS ROS ROS
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.114 HEADER LOG REGISTER 4 - OFFSET 128h
Bit
7:0 15:8 23:16 31:24
Function
Header Byte 15 Header Byte 14 Header Byte 13 Header Byte 12
Type
ROS ROS ROS ROS
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0
Page 124 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.5.115 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER - OFFSET 12Ch
Bit
0
Function
Target Abort on Split Completion Status Master Abort on Split Completion Status Received Target Abort Status Received Master Abort Status Reserved Unexpected Split Completion Error Status Uncorrectable Split Completion Message Data Error Status Uncorrectable Data Error Status Uncorrectable Attribute Error Status Uncorrectable Address Error Status Delayed Transaction Discard Timer Expired Status PERR_L Assertion Detected Status SERR_L Assertion Detected Status Internal Bridge Error Status Reserved
Type
RWCS
Description
Reset to 0
1
RWCS
Reset to 0
2 3 4 5
RWCS RWCS RO RWCS
Reset to 0 Reset to 0 Reset to 0 Reset to 0
6
RWCS
Reset to 0
7 8
RWCS RWCS
Reset to 0 Reset to 0
9 10
RWCS RWCS
Reset to 0 Reset to 0
11 12 13 31:14
RWCS RWCS RWCS RO
Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.116 SECONDARY UNCORRECTABLE ERROR MASK REGISTER - OFFSET 130h
Bit
0
Function
Target Abort on Split Completion Mask Master Abort on Split Completion Mask Received Target Abort Mask Received Master Abort Mask Reserved Unexpected Split Completion Error Mask Uncorrectable Split Completion Message Data Error Mask
Type
RWS
Description
Reset to 0
1
RWS
Reset to 0
2 3 4 5
RWS RWS RO RWS
Reset to 0 Reset to 1 Reset to 0 Reset to 1
6
RWS
Reset to 0
Page 125 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Bit
7 8 9 10
Function
Uncorrectable Data Error Mask Uncorrectable Attribute Error Mask Uncorrectable Address Error Mask Delayed Transaction Discard Timer Expired Mask PERR_L Assertion Detected Mask SERR_L Assertion Detected Mask Internal Bridge Error Mask Reserved
Type
RWS RWS RWS RWS
Description
Reset to 1 Reset to 1 Reset to 1 Reset to 1
11 12 13 31:14
RWS RWS RWS RO
Reset to 0 Reset to 1 Reset to 0 Reset to 0
7.5.117 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER - OFFSET 134h
Bit
0
Function
Target Abort on Split Completion Severity Master Abort on Split Completion Severity Received Target Abort Severity Received Master Abort Severity Reserved Unexpected Split Completion Error Severity Uncorrectable Split Completion Message Data Error Severity Uncorrectable Data Error Severity Uncorrectable Attribute Error Severity Uncorrectable Address Error Severity Delayed Transaction Discard Timer Expired Severity PERR_L Assertion Detected Severity SERR_L Assertion Detected Severity Internal Bridge Error Severity Reserved
Type
RWS
Description
Reset to 0
1
RWS
Reset to 0
2 3 4 5
RWS RWS RO RWS
Reset to 0 Reset to 0 Reset to 0 Reset to 0
6
RWS
Reset to 1
7 8
RWS RWS
Reset to 0 Reset to 1
9
RWS
Reset to 1
10
RWS
Reset to 0
11 12 13 31:14
RWS RWS RWS RO
Reset to 0 Reset to 1 Reset to 0 Reset to 0
Page 126 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.5.118 SECONDARY ERROR CAPABILITY AND CONTROL REGISTER - OFFSET 138h
Bit
4:0 31:5
Function
Secondary First Error Pointer Reserved
Type
ROW RO
Description
Reset to 0 Reset to 0
7.5.119 SECONDARY HEADER LOG REGISTER - OFFSET 13Ch - 148h
Bit
35:0
Function
Transaction Attribute Transaction Command Lower Transaction Command Upper
Type
ROS
Description
Transaction attribute, CBE [3:0] and AD [31:0] during attribute phase Reset to 0 Transaction command lower, CBE [3:0] during first address phase Reset to 0 Transaction command upper, CBE [3:0] during second address phase of DAC transaction Reset to 0 Reset to 0 Transaction address, AD [31:0] during first address phase Reset to 0 Transaction address, AD [31:0] during second address phase of DAC transaction Reset to 0
39:36
ROS
43:40
ROS
63:44 95:64
Reserved Transaction Address
ROS ROS
127:96
Transaction Address
ROS
7.5.120 RESERVED REGISTER - OFFSET 14Ch 7.5.121 VC CAPABILITY ID REGISTER - OFFSET 150h
Bit
15:0
Function
VC Capability ID
Type
RO
Description
Reset to 0002h
7.5.122 VC CAPABILITY VERSION REGISTER - OFFSET 150h
Bit
19:16
Function
VC Capability Version
Type
RO
Description
Reset to 1h
7.5.123 NEXT CAPABILITY OFFSET REGISTER - OFFSET 150h
Bit
31:20
Function
Next Capability Offset
Type
RO
Description
Next capability offset - the end of capabilities Reset to 0
Page 127 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.5.124 PORT VC CAPABILITY REGISTER 1 - OFFSET 154h
Bit
2:0 3 6:4 7 9:8 11:10 31:12
Function
Extended VC Count Reserved Low Priority Extended VC Count Reserved Reference Clock Port Arbitration Table Entry Size Reserved
Type
RO RO RO RO RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0
7.5.125 PORT VC CAPABILITY REGISTER 2 - OFFSET 158h
Bit
7:0 23:8 31:24
Function
VC Arbitration Capability Reserved VC Arbitration Table Offset
Type
RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0
7.5.126 PORT VC CONTROL REGISTER - OFFSET 15Ch
Bit
0 3:1 15:4
Function
Load VC Arbitration Table VC Arbitration Select Reserved
Type
RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0
7.5.127 PORT VC STATUS REGISTER - OFFSET 15Ch
Bit
16 31:17
Function
VC Arbitration Table Status Reserved
Type
RO RO
Description
Reset to 0 Reset to 0
7.5.128 VC0 RESOURCE CAPBILITY REGISTER - OFFSET 160h
Bit
7:0 13:8 14 15 22:16 23 31:24
Function
Port Arbitration Capability Reserved Advanced Packet Switching Reject Snoop Transactions Maximum Time Slots Reserved Port Arbitration Table Offset
Type
RO RO RO RO RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0 Reset to0 Reset to 0 Reset to 0 Reset to 0
Page 128 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.5.129 VC0 RESOURCE CONTROL REGISTER - OFFSET 164h
Bit
7:0 7:1 15:8 16 19:17 23:20 26:24 30:27 31
Function
TC / VC Map TC / VC Map Reserved Load Port Arbitration Table Port Arbitration Select Reserved VC ID Reserved VC Enable
Type
RO RW RO RO RO RO RO RO RO
Description
Reset to 1 Reset to 7Fh Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 0 Reset to 1
7.5.130 VC0 RESOURCE STATUS REGISTER - OFFSET 168h
Bit
0 1 31:2
Function
Port Arbitration Table 1 VC0 Negotiation Pending Reserved
Type
RO RO RO
Description
Reset to 0 Reset to 0 Reset to 0
7.5.131 RESERVED REGISTERS - OFFSET 16Ch TO 2FCh 7.5.132 EXTENDED GPIO DATA AND CONTROL REGISTER - OFFSET 300h
Bit
2:0 5:3 8:6 11:9 14:12 31:16
Function
Extended GPIO output Extended GPIO output Extended GPIO output enable Extended GPIO output enable Extended GPIO input Reserved
Type
RWC RWS RWC RWS RO RO
Description
GPIO [6:4] as output, write 1 to clear Reset to 0 GPIO [6:4] as output, write 1 to set Reset to 0 GPIO [6:4] enable, write 1 to clear Reset to 0 GPIO [6:4] enable, write 1 to set Reset to 0 GPIO [6:4] as input Reset to 0 Reset to 0
7.5.133 EXTRA GPI/GPO DATA AND CONTROL REGISTER - OFFSET 304h
Bit
3:0 7:4 11:8
Function
Extra GPO Extra GPO Extra GPO enable
Type
RWC RWS RWC
Description
GPO [3:0], write 1 to clear Reset to 0 GPO [3:0], write 1 to set Reset to 0 GPO [3:0] enable, write 1 to clear Reset to 0
Page 129 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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Bit
15:12 19:16 31:20
Function
Extra GPO enable Extra GPI Reserved
Type
RWS RO RO
Description
GPO [3:0] enable, write 1 to set Reset to 0 Extra GPI [3:0] Data Register Reset to 0 Reset to 0
7.5.134 RESERVED REGISTERS - OFFSET 308h TO 30Ch 7.5.135 REPLAY AND ACKNOWLEDGE LATENCY TIMERS - OFFSET 310h
Bit
11:0 12 15:13 29:16 30
Function
Replay Timer Replay Timer Enable Reserved Acknowledge Latency Timer Acknowledge Latency Timer Enable Reserved
Type
RW RW RO RW RO
Description
Replay Timer Reset to 0 Replay Timer Enable Reset to 0 Reset to 0 Acknowledge Latency Timer Reset to 0 Acknowledge Latency Timer Enable Reset to 0 Reset to 0
31
RO
7.5.136 RESERVED REGISTERS - OFFSET 314h TO FFCh
Page 130 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.6
CONTROL AND STATUS REGISTERS FOR NON-TRANSPARENT BRIDGE MODE
Control and Status Registers (CSRs) can be accessed by Memory or I/O transactions from both primary and secondary ports. The CSRs are defined and to be used along with configuration registers (see previous section 7.5 for details) for non-transparent bridge operations.
Register Type
RO ROS RW RWC RWS RWCS
Descriptions
Read Only Read Only and Sticky Read/Write Read/Write "1" to clear Read/Write and Sticky Read/Write "1" to clear and Sticky
7.6.1 7.6.2
RESERVED REGISTERS - OFFSET 000h TO 004h DOWNSTREAM MEMORY 2 TRANSLATED BASE REGISTER - OFFSET 008h
Bit
11:0 31:12
Function
Reserved Downstream Memory 2 Translated Base
Type
RO RW
Description
Reset to 000h Define the translated base address for downstream memory transactions whose initiator addresses fall into Downstream Memory 2 address range. The number of bits that are used for translated base is determined by its setup register (offset 00Ch) Reset to 00000h
7.6.3
DOWNSTREAM MEMORY 2 SETUP REGISTER - OFFSET 00Ch
Bit
0
Function
Type Selector
Type
RO
Description
0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range Reset to 00000h 0: Disable this Base Address Register 1: Enable this Base Address Register Reset to 0
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
11:4 30:12
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
Page 131 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2
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7.6.4
DOWNSTREAM MEMORY 3 TRANSLATED BASE REGISTER - OFFSET 010h
Bit
11:0 31:12
Function
Reserved Downstream Memory 3 Translated Base
Type
RO RW
Description
Reset to 000000 Define the translated base address for downstream memory transactions whose initiator addresses fall into Downstream Memory 3 address range. The number of bits that are used for translated base is determined by its setup register (offset 014h) Reset to 00000h
7.6.5
DOWNSTREAM MEMORY 3 SETUP REGISTER - OFFSET 014h
Bit
0
Function
Type Selector
Type
RO
Description
0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 00 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range Reset to 00000h 0: Disable this Base Address Register 1: Enable this Base Address Register Reset to 0
2:1
Address Type
RO (WS)
3
Prefetchable Control
RO (WS)
11:4 30:12
Reserved Base Address Register Size
RO RO (WS)
31
Base Address Register Enable
RO (WS)
7.6.6
DOWNSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER - OFFSET 018h
Bit
30:0
Function
Base Address Register Size
Type
RW
Description
0: Set the corresponding bit in the Upper 32-bit Base Address Register to read only 1: Set the corresponding bit in the Upper 32-bit Base Address Register to read/write in order to control the size of the address range Reset to 00000000h 0: Disable 64-bit Base Address Register 1: Enable 64-bit Base Address Register Reset to 0
31
Base Address Register Enable
RW)
7.6.7
RESERVED REGISTERS - OFFSET 01Ch TO 030h
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7.6.8
UPSTREAM MEMORY 3 SETUP REGISTER - OFFSET 034h
Bit
0
Function
Type Selector
Type
RO
Description
0: Memory space is requested Reset to 0 00: 32-bit address space 01: 64-bit address space Reset to 01 0: Non-prefetchable 1: Prefetchable Reset to 0 Reset to 00 0: Set the corresponding bit in the Base Address Register to read only 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range Reset to 00000h
2:1
Address Type
RO
3
Prefetchable Control
RW
11:4 31:12
Reserved Base Address Register Size
RO RW
7.6.9
UPSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER - OFFSET 038h
Bit
30:0
Function
Base Address Register Size
Type
RW
Description
0: Set the corresponding bit in the Upper 32-bit Base Address Register to read only 1: Set the corresponding bit in the Upper 32-bit Base Address Register to read/write in order to control the size of the address range Reset to 00000000h 0: Disable 64-bit Base Address Register 1: Enable 64-bit Base Address Register Reset to 0
31
Base Address Register Enable
RW
7.6.10 7.6.11
RESERVED REGISTERS - OFFSET 3Ch TO 4Ch LOOKUP TABLE OFFSET - OFFSET 50h
Bit
7:0
Function
Lookup Table Offset
Type
RW
Description
This register contains the byte offset of the Lookup Table Entry to be accessed for upstream memory 2. The access is initiated when the lookup Table Data Register is accessed. This register should be written first before any Lookup Table Data access. Reset to 00h Reset to 0
31:8
Reserved
RO
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7.6.12
LOOKUP TABLE DATA - OFFSET 054h
Bit
0
Function
Valid
Type
RW
Description
0: Invalid lookup 1: Valid lookup Reset to 0 Reset to 00 0: Memory address is non-prefetchable 1: Memory address is Reset to 0 Reset to 0h Data written or read from the Lookup Table at the offset specified in the Lookup Table Offset Register. When writing to this register, the data value is written to the specified Lookup Table entry. When reading from this register, the data reflects the data value from the specified Lookup Table entry. The bit [24:8] is Translated Base Register bit when the lookup table size is set to 256B range. The bit [24:8] is reserved when the lookup table size is set to 32MB range (see PCI configuration offset 68h for non-transparent mode). Reset to 0 Data written or read from the Lookup Table at the offset specified in the Lookup Table Offset Register. When writing to this register, the data value is written to a specific Lookup Table entry (CSR offset 100h - 1FFh). When reading from this register, the data reflects the data value from the specific Lookup Table entry. Reset to 0
2:1 3
Reserved Prefetchable
RO RW
7:4 24:8
Reserved Translated base or Reserved
RO RW/RO
31:25
Translated Base
RW
7.6.13
UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER - OFFSET 058h
Bit
31:0
Function
Upstream Page Boundary IRQ 0
Type
RWC
Description
Each interrupt request bit is correspondent to a page entry in the lower half of the Upstream Memory 2 range. Bit [0] is for the first page, and bit [31] is for the 32nd page. PI7C9X130 sets the appropriate bit when it successfully transfers data to or from the imitator that addresses the last Double Word in a page. PI7C9X130 initiates an interrupt request on secondary interface when the interrupt request bit is set and the corresponding Upstream Page Boundary IRQ 0 Mask bit is reset. When forward bridge, PI7C9X130 asserts INTA_L or generates MSI on secondary bus (PCI interface). When reverse bridge, PI7C9X130 sends INTA_L assertion message or generates MSI on secondary interface (PCI Express). When writing a "1" to this register, it clears the corresponding interrupt request bit. Reset to 0
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7.6.14
UPSTREAM PAGE BOUNDARY IRQ 1 REQUEST REGISTER - OFFSET 05Ch
Bit
31:0
Function
Upstream Page Boundary IRQ 1
Type
RWC
Description
Each interrupt request bit is correspondent to a page entry in the lower half of the Upstream Memory 2 range. Bit [0] is for the 33rd page, and bit [31] is for the 64th page. PI7C9X130 sets the appropriate bit when it successfully transfers data to or from the initiator that addresses the last Double Word in a page. PI7C9X130 initiates an interrupt request on secondary interface when the interrupt request bit is set and the corresponding Upstream Page Boundary IRQ 1 Mask bit is reset. When forward bridge, PI7C9X130 asserts INTA_L or generates MSI on secondary bus (PCI interface). When reverse bridge, PI7C9X130 sends INTA_L assertion message or generates MSI on secondary interface (PCI Express). When wrting a "1" to this register, it clears the corresponding interrupt request bit. Reset to 0
7.6.15
UPSTREAM PAGE BOUNDARY IRQ 0 MASK REGISTER - OFFSET 060h
Bit
31:0
Function
Upstream Page Boundary IRQ 0 Mask
Type
RWC
Description
0: PI7C9X130 can initiate an interrupt request when the correspondent request bit is set 1: PI7C9X130 cannot initiate any interrupt request even though the correspondent request bit is set Reset to FFFFFFFFh
7.6.16
UPSTREAM PAGE BOUNDARY IRQ 1 MASK REGISTER - OFFSET 064h
Bit
31:0
Function
Upstream Page Boundary IRQ 1 Mask
Type
RWC
Description
0: PI7C9X130 can initiate an interrupt request when the correspondent request bit is set 1: PI7C9X130 cannot initiate any interrupt request even though the correspondent request bit is set Reset to FFFFFFFFh
7.6.17
RESERVED REGISTER - OFFSET 068C
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7.6.18
PRIMARY CLEAR IRQ REGISTER - OFFSET 070h
Bit
15:0
Function
Primary Clear IRQ
Type
RWC
Description
When writing "1" to this register bit, it clears the correspondent interrupt request bit. When reading this register, it returns the interrupt request bit status: 0: It is not the bit that causes the interrupt request on primary interface 1: It is the bit that causes the interrupt request on primary interface
Reset to 0000h
7.6.19
SECONDARY CLEAR IRQ REGISTER - OFFSET 070h
Bit
31:16
Function
Secondary Clear IRQ
Type
RWC
Description
When writing "1" to this register bit, it clears the correspondent interrupt request bit. When reading this register, it returns the interrupt request bit status: 0: It is not the bit that causes the interrupt request on secondary interface 1: It is the bit that causes the interrupt request on secondary interface
Reset to 0000h
7.6.20
PRIMARY SET IRQ REGISTER - OFFSET 074h
Bit
15:0
Function
Primary Set IRQ
Type
RWS
Description
When writing "1" to this register bit, it set the correspondent interrupt request bit. When reading this register, it returns the interrupt request bit status: 0: It is not the bit that causes the interrupt request on primary interface 1: It is the bit that causes the interrupt request on primary interface
Reset to 0000h
7.6.21
SECONDARY SET IRQ REGISTER - OFFSET 074h
Bit
31:16
Function
Secondary Set IRQ
Type
RWS
Description
When writing "1" to this register bit, it set the correspondent interrupt request bit. When reading this register, it returns the interrupt request bit status: 0: It is not the bit that causes the interrupt request on secondary interface 1: It is the bit that causes the interrupt request on secondary interface
Reset to 0000h
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7.6.22
PRIMARY CLEAR IRQ MASK REGISTER - OFFSET 078h
Bit
15:0
Function
Primary Clear IRQ Mask
Type
RWS
Description
When writing "1" to this register bit, it clears the correspondent interrupt request mask bit. When reading this register, it returns the primary Clear IRQ Mask bit status: 0: It allows to clear an interrupt request on primary interface 1: It does not allow to clear any interrupt request on primary interface Reset to FFFFh
7.6.23
SECONDARY CLEAR IRQ MASK REGISTER - OFFSET 078h
Bit
31:16
Function
Secondary Clear IRQ Mask
Type
RWS
Description
When writing "1" to this register bit, it clears the correspondent interrupt request mask bit. When reading this register, it returns the Secondary Clear IRQ Mask bit status: 0: It allows to clear an interrupt request on secondary interface 1: It does not allow to clear any interrupt request on secondary interface Reset to FFFFh
7.6.24
PRIMARY SET IRQ MASK REGISTER - OFFSET 07Ch
Bit
15:0
Function
Primary Set IRQ Mask
Type
RWS
Description
When writing "1" to this register bit, it set the correspondent interrupt request mask bit. When reading this register, it returns the Primary Set IRQ Mask bit status: 0: It allows to set an interrupt request on primary interface 1: It does not allow to set any interrupt request on primary interface
Reset to FFFFh
7.6.25
SECONDARY SET IRQ MASK REGISTER - OFFSET 07Ch
Bit
31:16
Function
Secondary Set IRQ Mask
Type
RWC
Description
When writing "1" to this register bit, it set the correspondent interrupt request mask bit. When reading this register, it returns the Secondary Set IRQ Mask bit status: 0: It allows to set an interrupt request on secondary interface 1: It does not allow to set any interrupt request on secondary interface Reset to FFFFh
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7.6.26 7.6.27
RESERVED REGISTERS - OFFSET 080h TO 09Ch SCRATCHPAD 0 REGISTER - OFFSET 0A0h
Bit
31:0
Function
Scratchpad 0
Type
RW
Description
The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.28
SCRATCHPAD 1 REGISTER - OFFSET 0A4h
Bit
31:0
Function
Scratchpad 1
Type
RW
Description
The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.29
SCRATCHPAD 2 REGISTER - OFFSET 0A8h
Bit
31:0
Function
Scratchpad 2
Type
RW
Description
The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.30
SCRATCHPAD 3 REGISTER - OFFSET 0ACh
Bit
31:0
Function
Scratchpad 3
Type
RW
Description
The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
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7.6.31
SCRATCHPAD 4 REGISTER - OFFSET 0B0h
Bit
31:0
Function
Scratchpad 4
Type
RW
Description
The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.32
SCRATCHPAD 5 REGISTER - OFFSET 0B4h
Bit
31:0
Function
Scratchpad 5
Type
RW
Description
The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.33
SCRATCHPAD 6 REGISTER - OFFSET 0B8h
Bit
31:0
Function
Scratchpad 6
Type
RW
Description
The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.34
SCRATCHPAD 7 REGISTER - OFFSET 0BCh
Bit
31:0
Function
Scratchpad 7
Type
RW
Description
The scratchpad is a 32-bit internal register that can be accessed from both primary and secondary interfaces. The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h
7.6.35
RESERVED REGISTERS - OFFSET 0C0h TO 0FCh
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7.6.36
LOOKUP TABLE REGISTERS - OFFSET 100h TO 1FCh
Bit
2047:0
Function
Lookup Table
Type
RW
Description
The lookup table has 64 entries. Each entry has 32-bit mapped to each page of the Upstream Memory 2 base address range 64th page: bit [2047:2016] 62nd page: bit [1983:1952] 60th page: bit [1919:1888] 58th page: bit [1855:1824] 56th page: bit [1791:1760] 54th page: bit [1727:1696] 52nd page: bit [1663:1632] 50th page: bit [1599:1568] 48th page: bit [1535:1504] 46th page: bit [1471:1440] 44th page: bit [1407:1376] 42nd page: bit [1343:1312] 40th page: bit [1279:1248] 38th page: bit [1215:1184] 36th page: bit [1151:1120] 34th page: bit [1087:1056] 32nd page: bit [1023:992] 30th page: bit [959:928] 28th page: bit [895:864] 26th page: bit [831:800] 24th page: bit [767:736] 22nd page: bit [703:672] 20th page: bit [639:608] 18th page: bit [575:544] 16th page: bit [511:480] 14th page: bit [447:416] 12th page: bit [382:352] 10th page: bit [319:288] 8th page: bit [255:224] 6th page: bit [191:160] 4th page: bit [127:96] 2nd page: bit [63:32] 63rd page: bit [2015:1984] 61st page: bit [1951:1920] 59th page: bit [1887:1856] 57th page: bit [1823:1792] 55th page: bit [1759:1728] 53rd page: bit [1695:1664] 51st page: bit [1631:1600] 49th page: bit [1567:1536] 47th page: bit [1503:1472] 45th page: bit [1439:1408] 43rd page: bit [1375:1344] 41st page: bit [1311:1280] 39th page: bit [1247:1216] 37th page: bit [1183:1152] 35th page: bit [1119:1088] 33rd page: bit [1055:1024] 31st page: bit [991:960] 29th page: bit [927:896] 27th page: bit [863:832] 25th page: bit [799:768] 23rd page: bit [735:704] 21st page: bit [671:640] 19th page: bit [607:576] 17th page: bit [543:512] 15th page: bit [479:448] 13th page: bit [415:383] 11th page: bit [351:320] 9th page: bit [287:256] 7th page: bit [223:192] 5th page: bit [159:128] 3rd page: bit [95:64] 1st page: bit [31:0]
Reset to unknown
7.6.37
RESERVED REGISTERS - OFFSET 200h TO FFCh
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8
GPIO PINS AND SM BUS ADDRESS
GPIO [3:1] of PI7C9X130 are defined for hot-plug usage if MSK_IN=1 during Reset. Please see configuration register definition (offset 78h - 7Bh). GPIO [3:0] are also defined the address bits of SMBUS device ID if SM Bus is selected (TM1=1). The address-strapping table of SMBUS with GPIO [3:0] pins is defined in the following table: Figure 8-1 SM Bus Device ID Strapping
SM Bus Address Bit
Address bit [7] Address bit [6] Address bit [5] Address bit [4] Address bit [3] Address bit [2] Address bit [1]
SM Bus device ID
=1 =1 =0 = GPIO [3] = GPIO [2] = GPIO [1] = GPIO [0]
GPIO [3:0] pins can be further defined to serve other functions in the next generation Device. Four GPI [3:0] and four GPO [3:0] have been added to PI7C9X130 when external arbiter is selected (CFN_L=1). If external arbiter is selected, REQ_L [5:2] and GNT [5:2] will become the GPI [3:0] and GPO [3:0] respectively.
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9
CLOCK SCHEME
PCI Express interface: PI7C9X130 requires 100MHz differential clock inputs through REFCLKP and REFCLKN Pins. PCI-X / PCI interface: To use external clock source, PI7C9X130 requires PCI-X clock (up to 133MHz) to be connected to the Pin T6, CLKIN / M66EN. PI7C9X130 uses the CLKIN and generates seven clock outputs, CLKOUT [6:0]. Also, PI7C9X130 requires one of the CLKOUT [6:0] (preferably CLKOUT [6]) to be connected to FBCLKIN for the PCI-X interface logic of PI7C9X130. To enable internal clock generator and auto frequency detection, CLKIN / M66EN needs to connect to M66EN of a PCIX / PCI compliant device. The CLK / M66EN input pin is driven high or low to enable the internal clock generator and auto frequency detection. The frequency output of CLKOUT[0:6] is determined by the state of CLKIN (M66EN), PCIXCAP, PCIXUP and SEL100 listed as below: CLKIN (M66EN) low low high high dont care dont care dont care dont care PCIXCAP gnd gnd gnd gnd 10K to gnd 10K to gnd high high SEL100 high low high low high low High low Frequency PCI 25 Mhz PCI 33 Mhz PCI 50 Mhz PCI 66 Mhz PCIX 50 Mhz PCIX 66 Mhz PCIX 100 Mhz PCIX 133 Mhz
The actual number of masters supported will vary depending on the loading of the PCI-X bus. Typically, PI7C9X130 can support up to one 133MHz PCI-X slot or two 66MHz PCI-X slots.
The PI7C9X130 PCI Clock Outputs, CLKOUT [6:0], can be enabled or disabled through the configuration register.
10
INTERRUPTS
PI7C9X130 supports interrupt message packets on PCIe side. PI7C9X130 supports PCI interrupt (INTA, B, C, D) pins or MSI (Message Signaled Interrupts) on PCI side. PCI interrupts and MSI are mutually exclusive. In order words, if MSI is enabled, PCI interrupts will be disabled. PI7C9X130 support 64-bit addressing MSI. In reverse bridge mode, PI7C9X130 maps the interrupt message packets to PCI interrupt pins or MSI if MSI is enable (see configuration register bit [16] of Offset F0h). In forward bridge mode, PI7C9X130 maps the PCI interrupts pins or MSI if enable on PCI side to interrupt message packets on PCIe side.
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There are eight interrupt message packets. They are Assert_INTA, Assert_INTB, Assert_INTC, Assert_INTD, Deassert_INTA, Deassert_INTB, Deassert_INTC, and Deassert_INTD. These eight interrupt messages are mapped to the four PCI interrupts (INTA, INTB, INTC, and INTD). See table 101 for interrupt mapping information in reverse bridge mode. PI7C9X130 tracks the PCI interrupt (INTA, INTB, INTC, and INTD) pins and maps them to the eight interrupt messages. See table 10-2 for interrupt mapping information in forward bridge mode. Figure 10-1 PCIe Interrupt Messages to PCI Interrupts Mapping in Reverse Bridge Mode
PCIe Interrupt messages (from sources of interrupt)
INTA message INTB message INTC message INTD message
PCI Interrupts (to host controller)
INTA INTB INTC INTD
Figure 10-2 PCI Interrupts to PCIe Interrupt Messages Mapping in Forward Bridge Mode
PCI Interrupts (from sources of interrupts)
INTA INTB INTC INTD
PCIe Interrupt message packets (to host controller)
INTA message INTB message INTC message INTD message
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11
EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS
EEPROM (I2C) INTERFACE
PI7C9X130 supports EEPROM interface through I2C bus. In EEPROM interface, pin A2 is the EEPROM clock (SCL) and pin A1 is the EEPROM data (SDL). When TM2 is strapped to low, TM1 selects EEPROM interface or System Management Bus. To select EEPROM (I2C) interface, TM1 needs to be set to low. When EEPROM interface is selected, SCL is an output. SCL is the I2C bus clock to the I2C device. In addition, SDL is a bi-directional signal for sending and receiving data.
11.1
11.2
SYSTEM MANAGEMENT BUS
PI7C9X130 supports SM bus protocol if TM1=1 when TM2 is strapped to low. In addition, SMBCLK (pin A2) and SMBDAT (pin A1) are utilized as the clock and data pins respectively for the SM bus. When SM bus interface is selected, SMBCLK pin is an input for the clock of SM bus and SMBDAT pin is an open drain buffer that requires external pull-up resistor for proper operation.
12
HOT PLUG OPERATION
PI7C9X130 is not equipped with standard hot-plug controller (SHPC) integrated. However, PI7C9X130 supports hot-plug signaling messages and registers to simplify the implementation of hot-plug system. Using PI7C9X130 on motherboard: PI7C9X130 supports hot-plug on PCI bus if forward bridging is selected (REVRSB=0). PI7C9X130 supports hot-plug function on PCI Express bus when reverse bridge mode is selected (REVRSB=1). Using PI7C9X130 on add-in card: PI7C9X130 supports hot-plug on PCI Express bus in forward bridge mode. Hot-plug messages will be generated by PI7C9X130 based on the add-in card conditions. PI7C9X130 supports hot-plug function on PCI bus when reverse bridge mode is selected. PI7C9X130 will tri-state the PCI bus when RESET is asserted. Also, PI7C9X130 will de-assert INTA_L if RESET is asserted. The state machine of PI7C9X130 PCI bus interface will remain idle if the RESET is asserted. After RESET is de-asserted, PI7C9X130 will remain in idle state until an address phase containing a valid address for PI7C9X130 or its downstream devices. PI7C9X130 expects the REFCLK signal will be provided to its upstream PCI Express Port prior to the de-assertion of RESET. The Downstream PCI Port of PI7C9X130 supports a range of frequency up to 66MHz.
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PI7C9X130 also supports subsystem vendor and subsystem ID. PI7C9X130 will ignore target response while the bus is idle. PRSNT1# and PRSNT2# are not implemented on both PI7C9X130. The use of these two signals is mandatory on an add-in card in order to support hot-plug.
13
RESET SCHEME
PI7C9X130 requires the fundamental reset (PERST_L) input for internal logic when it is set as forward bridge mode. PI7C9X130 requires the PCI/PCI-X reset (RESET_L) input when it is set as reverse bridge mode. Also, PI7C9X130 has a power-on-reset (POR) circuit to detect VDDCAUX power supply for auxiliary logic control. Cold Reset: A cold reset is a fundamental or power-on reset that occurs right after the power is applied to PI7C9X130 (during initial power up). See section 7.1.1 of PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 for details. Warm Reset: A warm reset is a reset that triggered by the hardware without removing and re-applying the power sources to PI7C9X130. Hot Reset: A hot reset is a reset that used an in-band mechanism for propagating reset across a PCIe link to PI7C9X130. PI7C9X130 will enter to training control reset when it receives two consecutive TS1 or TS2 order-sets with reset bit set. DL_DOWN Reset: If the PCIe link goes down, the Transaction and Data Link Layer will enter DL_DOWN status. PI7C9X130 discards all transactions and returns all logic and registers to initial state except the sticky registers. Upon receiving reset (cold, warm, hot, or DL_DOWN) on PCIe interface, PI7C9X130 will generate PCI/PCI-X reset (RESET_L) to the downstream devices on the PCI/PCI-X bus in forward bridge mode. The PCI/PCI-X reset de-assertion follows the de-assertion of the reset received from PCIe interface. The reset bit of Bridge Control Register may be set depending on the application. PI7C9X130 will tolerant to receive and process SKIP order-sets at an average interval between 1180 to 1538 Symbol Times. PI7C9X130 does not keep PCI/PCI-X reset active when VD33 power is off even though VAUX (3.3v) is supported. It is recommended to add a weak pull-down resistor on its application board to ensure PCI/PCI-X reset is low when VD33 power is off (see section 7.3.2 of PCI Bus Power management Specification Revision 1.1). In reverse bridge mode, PI7C9X130 generates fundamental reset (PERST_L) and then 1024 TS1 ordersets with reset bit set when PCI/PCI-X reset (RESET_L) is asserted to PI7C9X130. PI7C9X130 has scheduling skip order-set for insertion at an interval between 1180 and 1538 Symbol Times. PI7C9X130 transmits one Electrical Idle order-set and enters to Electrical Idle.
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14
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI7C9X130 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins. The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the PCI resource is operating PCI bus cycles.
14.1
INSTRUCTION REGISTER
PI7C9X130 implements a 5-bit Instruction register to control the operation of the JTAG logic. The defined instruction codes are shown in Table 14-1. Those bit combinations that are not listed are equivalent to the BYPASS (11111) instruction: Figure 14-1 Instruction Register Codes
Instruction
EXTEST SAMPLE HIGHZ CLAMP IDCODE
Operation Code (binary)
00000 00001 00101 00100 01100
Register Selected
Boundary Scan Boundary Scan Bypass Bypass Device ID
Operation
Drives / receives off-chip test data Samples inputs / pre-loads outputs Tri-states output and I/O pins except TDO pin Drives pins from boundary-scan register and selects Bypass register for shifts Accesses the Device ID register, to read manufacturer ID, part number, and version number Selected Bypass Register Scan test Memory BIST test
BYPASS INT_SCAN MEM_BIST
11111 00010 01010
Bypass Internal Scan Memory BIST
14.2
BYPASS REGISTER
The required bypass register (one-bit shift register) provides the shortest path between TDI and TDO when a bypass instruction is in effect. This allows rapid movement of test data to and from other components on the board. This path can be selected when no test operation is being performed on the PI7C9X130.
14.3
DEVICE ID REGISTER
This register identifies Pericom as the manufacturer of the device and details the part number and revision number for the device.
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Figure 14-2 JTAG Device ID Register
Bit
31:28 27:12 11:1 0
Type
RO RO RO RO
Value
00h E130h 23Fh 1b
Description
Version number Last 4 digits (hex) of the die part number Pericom identifier assigned by JEDEC Fixed bit equal to 1'b1
14.4
BOUNDARY SCAN REGISTER
The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by connected the internal signal of the PI7C9X130 package pins. The VDD, VSS, and JTAG pins are not in the boundary scan chain. The input to the shift register is TDI and the output from the shift register is TDO. There are 4 different types of boundary scan cells, based on the function of each signal pin. The boundary scan register cells are dedicated logic and do not have any system function. Data may be loaded into the boundary scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory SAMPLE and EXTEST instructions. Parallel loading takes place on the rising edge of TCK.
14.5
JTAG BOUNDARY SCAN REGISTER ORDER
Table 14-1 JTAG Boundary Scan Register Definition
Boundary Scan Register Number
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
Pin Name
GPIO [6] AD [0] AD [1] AD [2] AD [3] AD [4] AD [5] AD [6] AD [7] CBE [0] -
Ball Location
L15 L16 K13 K14 K15 K16 J13 J14 J15 J16 -
Type
BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL
Tri-state Control Cell
1 3 5 7 9 11 13 15 17 19 -
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Boundary Scan Register Number
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
Pin Name
AD [8] AD [9] AD [10] AD [11] AD [12] AD [13] AD [14] AD [15] CBE [1] PAR SERR_L PERR_L LOCK_L SEL100 DEV64 ACK64_L REQ64_L PAR64 AD [47] AD [46] AD [45] AD [44] AD [43] AD [42] AD [41] AD [40]
Ball Location
H13 H14 H15 H16 G13 G14 G15 G16 F13 F14 F15 F16 E13 E14 E15 E16 D14 D15 D16 C15 C16 B16 B15 A15 C14 B14
Type
BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL INPUT INPUT BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR
Tri-state Control Cell
21 23 25 27 29 31 33 35 37 39 41 43 45 49 51 53 55 57 59 61 63 65 67 69
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Boundary Scan Register Number
69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
Pin Name
CBE [5] AD [39] AD [38] AD [37] AD [36] AD [35] AD [34] AD [33] AD [32] CBE [4] STOP_L DEVSEL_L TRDY_L IRDY_L FRAME_L CBE [2] AD [16] AD [17] AD [18] AD [19] AD [20] AD [21] AD [22] AD [23] CBE [3]
Ball Location
A14 C13 B13 A13 D12 C12 B12 A12 D11 C11 B11 A11 D10 C10 B10 A10 D9 C9 B9 A9 D8 C8 B8 A8 D7
Type
CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTRL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR
Tri-state Control Cell
71 73 75 77 79 81 83 85 87 89 91 93 93 96 98 100 102 104 106 108 110 112 114 116 118
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Boundary Scan Register Number
118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166
Pin Name
AD [24] AD [25] AD [26] AD [27] AD [28] AD [29] AD [30] AD [31] PME_L SMBCLK SMBDAT CLKRUN_L FBCLKIN PCIXCAP PCIXUP PERST_L REQ_L [0] REQ_L [1] REQ_L [2] REQ_L [3] REQ_L [4] REQ_L [5] HSEN HSSW INTA_L GNT_L [0] GNT_L [1] GNT_L [2] GNT_L [3] GNT_L [4] GNT_L [5] -
Ball Location
C7 B7 A7 D6 C6 B6 A6 D5 C5 B5 A5 C4 B4 A4 B3 P1 R1 P2 R2 T2 N3 P3 R3 T3 P4 R4 T4 N5 P5 R5 T5 -
Type
CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL INPUT INPUT OUTPUT3 CONTROL BIDIR CONTROL INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT BIDIR CONTROL OUTPUT3 CONTROL OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 CONTROL
Tri-state Control Cell
120 122 124 126 128 130 132 134 136 138 140 142 146 148 158 160 166 166 166 166 166 -
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Boundary Scan Register Number
167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215
Pin Name
LOO ENUM_L INTB_L CLKIN / M66EN RESET_L CFN_L GPIO [3] GPIO [2] GPIO [1] GPIO [0] CLKOUT [0] CLKOUT [1] CLKOUT [2] CLKOUT [3] CLKOUT [4] CLKOUT [5] CLKOUT [6] GPIO [4] GPIO [5] INTC_L AD [63] AD [62] AD [61] AD [60] AD [59] AD [58] AD [57] AD [56] CBE [7]
Ball Location
N6 P6 R6 T6 N7 P7 R7 T7 N8 P8 R8 T8 N9 P9 R9 T9 N10 P10 R10 T10 N11 P11 R11 T11 N12 P12 R12 T12 P13
Type
OUTPUT3 CONTROL OUTPUT3 CONTROL BIDIR CONTROL INPUT BIDIR CONTROL INPUT BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT3 CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR
Tri-state Control Cell
168 170 172 175 178 180 182 184 192 192 192 192 192 192 192 194 196 198 200 202 204 206 208 210 212 214 216
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Boundary Scan Register Number
216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239
Pin Name
AD [55] AD [54] AD [53] AD [52] AD [51] AD [50] AD [49] AD [48] CBE [6] REVRSB INTD_L MSK_IN IDSEL
Ball Location
R13 T13 P14 R14 T14 T15 R15 R16 P15 N14 N15 N16 M13
Type
CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL BIDIR CONTROL INPUT BIDIR CONTROL INPUT INPUT
Tri-state Control Cell
218 220 222 224 226 228 230 232 234 237 -
15
POWER MANAGEMENT
PI7C9X130 supports D0, D3-hot, D3-cold Power States. D1 and D2 states are not supported. The PCI Express Physical Link Layer of the PI7C9X130 device supports the PCI Express Link Power Management with L0, L0s, L1, L2/L3 ready and L3 Power States. For the PCI Port of PI7C9X130, it supports the standard PCI Power Management States with B0, B1, B2 and B3. During D3-hot state, the main power supplies of VDDP, VDDC, and VD33 can be turned off to save power while keeping the VDDAUX, VDDCAUX, and VAUX with the auxiliary power supplies to maintain all necessary information to be restored to the full power D0 state. PI7C9X130 has been designed to have sticky registers that are powered by auxiliary power supplies. PME_L pin allows PCI devices to request power management state changes. Along with the operating system and application software, PCI devices can achieve optimum power saving by using PME_L in forward bridge mode. PI7C9X130 converts PME_L signal information to power management messages to the upstream switches or root complex. In reverse bridge mode, PI7C9X130 converts the power management event messages from PCIe devices to the PME_L signal and continues to request power management state change to the host bridge. PI7C9X130 also supports ASPM (Active State Power Management) to facilitate the link power saving. PI7C9X130 supports beacon generation but does not support WAKE# signal.
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16
16.1
ELECTRICAL AND TIMING SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table 16-1 Absolute Maximum Ratings
Storage Temperature Ambient Temperature with power appiled PCI Express supply voltage to ground potential (VDDA, VDDP, VDDC, VDDAUX, and VDDCAUX) PCI supply voltage to ground potential (VD33 and VAUX) DC input voltage for PCI Express signals DC input voltage for PCI signals -65oC to 150oC 0oC to 85oC -0.3v to 3.0v -0.3v to 3.6v -0.3v to 3.0v -0.5v to 5.75v
16.2
DC SPECIFICATIONS
Table 16-2 provides DC Electrical Characteristics of PI7C9X130: Table 16-2 DC Electrical Characteristics
Power Pins VDDA VDDP VDDAUX VTT VDDA_PLL VDDP_PLL VDDC VDDCAUX VD33 VAUX Min. 1.6v 1.6v 1.6v VDDP 1.6v 1.6v 1.6v 1.6v 3.0v 3.0v Typ. 1.8v 1.8v 1.8v VDDP 1.8v 1.8v 1.8v 1.8v 3.3v 3.3v Max. 2.0v 2.0v 2.0v 2.0v 2.0v 2.0v 2.0v 2.0v 3.6v 3.6v
VDDA: analog power for PCI Express Interface VDDP: digital power for PCI Express Interface VDDAUX: digital auxiliary power for PCI Express Interface VTT: termination power for PCI Express Interface VDDA_PLL: analog power for PLL of PCI-X interface VDDP_PLL: digital power for PLL of PCI-X interface VDDC: digital power for the core VDDCAUX: digital auxiliary power for the core VD33: digital power for PCI/PCI-X interface VAUX: digital auxiliary power for PCI/PCI-X interface In order to support auxiliary power management fully, it is recommended to have VDDP and VDDAUX separated. By the same token, VD33/VDDC and VAUX/VDDCAUX need to be separated for auxiliary
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power management support. However, if auxiliary power management is not required, VD33 and VDDC can be connected to VAUX and VDDCAUX respectively. The typical power consumption of PI7C9X130 is about 1.5 watt. PI7C9X130 is capable of sustaining 2000V human body model and 500V charged device model for the ESD protection without any damages.
16.3
AC SPECIFICATIONS
Table 16-3 provides PCI Bus Timing Parameters of PI7C9X130. Table 16-3 PCI Bus Timing Parameters
Symbol Parameter PCI-X 133MHz Min. Max. 1.2 1.2 0.5 0.7 0.7 0 3.8 3.8 7 PCI 66 MHz Min. Max. 3 5 0 2 2 2 6 6 14 PCI 33 MHz Min. Max. 7 10, 124 0 2 2 2 11 12 28 ns Units
Tsu Tsu (ptp) Th Tval Tval (ptp) Ton Toff
Input setup time to CLK - bused signals 1,2,3 Input setup time to CLK - point-to-point 1,2,3 Input signal hold time from CLK 1,2 CLK to signal valid delay - bused signals 1,2,3 CLK to signal valid delay - point-to-point 1,2,3 Float to active delay 1,2 Active to float delay 1,2
1. See Figure 16 -1 PCI Signal Timing Measurement Conditions. 2. All PCI interface signals are synchronized to FBCLKIN. 3. Point-to-point signals are REQ_L [7:0], GNT_L [7:0], LOO, and ENUM_L. Bused signals are AD, CBE, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, LOCK_L, STOP_L and IDSEL. 4. PCI Control Signals: FRAME_L, TRDY_L, IRDY_L, DEVSEL_L, STOP_L, SERR_L, PERR_L, LOCK_L, INTA_L, INTB_L, INTC_L, INTD_L, REQ64_L and ACT64_L of PI7C9X130 require pullup resistors (~5K ohm) if PI7C9X130 is implemented as a PCIX host on the system motherboard. 5. If the system needs to support 32-bit PCI add-in card then AD[63::32] and C/BE[7::4]_L pins need pull-up resistor (~5K ohm) 6. REQ_L signals have a setup of 10ns and GNT_L signals have a setup of 12ns.
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Figure 16-1 PCI Signal Timing Conditions
17
PACKAGE INFORMATION
Figure 17-1 Top View Drawing
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Figure 17-2 Bottom View Drawing
The package of PI7C9X130 is a 17mm x 17mm PBGA (256 Pin) package. The ball pitch is 1.0mm and the ball size is 0.5mm. The following are the package information and mechanical dimension:
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Figure 17-3 Package Outline Drawing
18
ORDERING INFORMATION
Device PI7C9X130CNDE Package 256-pin PBGA 17 x 17mm RoHS Compliant Yes Temperature Range -40C to 85C
Page 157 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2

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